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Some coreboot project code with my work
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Author
2017-05-20
nb/intel/sandybridge: Use macros to determine min and max of timA
Arthur Heymans
2017-05-19
nb/intel/sandybridge: Hide additional nb devices
Patrick Rudolph
2017-05-05
nb/intel/sandybridge/early_init: Use register name
Patrick Rudolph
2017-05-05
nb/intel/sandybridge/romstage: Use register name
Patrick Rudolph
2017-05-01
nb/intel/sandybridge/gma: Set up OpRegion in nb code
Patrick Rudolph
2017-04-07
nb/intel/sandybridge/raminit: Fix odt stretch
Patrick Rudolph
2017-04-07
nb/intel/sandybridge/raminit: Always run quick_ram_check
Patrick Rudolph
2017-04-07
nb/intel/sandybridge/raminit: Reduce log level
Patrick Rudolph
2017-04-07
nb/intel/sandybridge/raminit: Fix normalize_training
Patrick Rudolph
2017-04-04
nb/intel/sandybridge/raminit: Add default values
Patrick Rudolph
2017-04-04
nb/intel/sandybridge/raminit: Add debugging output
Patrick Rudolph
2017-04-04
nb/intel/sandybridge/raminit: Add 100MHz refclock support
Patrick Rudolph
2017-04-04
nb/intel/sandybridge/raminit: Use Ivy Bridge specific values
Patrick Rudolph
2017-04-03
nb/intel: Deduplicate vbt header
Patrick Rudolph
2017-03-28
vboot: Select SoC-specific configuration for all Chrome OS boards
Julius Werner
2017-03-27
nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings
Arthur Heymans
2017-01-06
nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>
Arthur Heymans
2016-12-16
nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge
Patrick Rudolph
2016-12-09
intel/sandybridge: Use postcar_frame for MTRR setup
Kyösti Mälkki
2016-12-08
nb/intel/sandybridge: Lock PAVPC
Dennis Wassenberg
2016-12-07
MMCONF_SUPPORT: Drop redundant logging
Kyösti Mälkki
2016-12-07
MMCONF_SUPPORT: Consolidate resource registration
Kyösti Mälkki
2016-12-07
MMCONF_SUPPORT: Flip default to enabled
Kyösti Mälkki
2016-12-07
PCI ops: MMCONF_SUPPORT_DEFAULT is required
Kyösti Mälkki
2016-12-06
CPU: Declare cpu_phys_address_size() for all arch
Kyösti Mälkki
2016-12-06
intel PCI ops: Remove explicit PCI MMCONF access
Kyösti Mälkki
2016-12-05
nb/intel/sandybridge/raminit: Split raminit.c
Patrick Rudolph
2016-12-01
romstage_handoff: remove code duplication
Aaron Durbin
2016-11-29
nb/intel/nehalem,sandybridge: Hook up libgfxinit
Nico Huber
2016-11-29
nb/intel/sandybridge/raminit: Support CL > 11
Patrick Rudolph
2016-11-28
nb/intel/sandybridge/raminit: Reset internal state on fallback attempts
Patrick Rudolph
2016-11-22
nb/intel/sandybridge/raminit: Do not log inside busy-wait loop
Kyösti Mälkki
2016-11-22
Remove explicit select MMCONF_SUPPORT
Kyösti Mälkki
2016-11-21
nb/intel: Fix some spelling mistakes in comments and strings
Martin Roth
2016-11-20
intel sandy/ivy: Improve DIMM replacement detection
Kyösti Mälkki
2016-11-20
intel sandy/ivy: Skip SPD loading on S3 resume path
Kyösti Mälkki
2016-11-20
intel sandy/ivy: Move SPD loading after TS_BEFORE_INITRAM
Kyösti Mälkki
2016-11-20
intel sandy/ivy: Change CRC used to detect DIMM replacement
Kyösti Mälkki
2016-11-20
nb/intel/sandybridge/raminit: Fix disable_channel
Patrick Rudolph
2016-11-20
nb/intel/sandybridge/raminit: Find CMD rate per channel
Patrick Rudolph
2016-11-20
nb/intel/sandybridge/raminit: Define registers
Patrick Rudolph
2016-11-20
nb/intel/sandybridge/raminit: Get rid of fallback attempts
Patrick Rudolph
2016-11-20
nb/intel/sandybridge/raminit: Fix CAS Write Latency
Patrick Rudolph
2016-11-18
intel/sandybridge: Use romstage_handoff for S3
Kyösti Mälkki
2016-11-18
intel/sandybridge post-car: Redo MTRR settings and stack selection
Kyösti Mälkki
2016-11-11
intel post-car: Separate files for setup_stack_and_mtrrs()
Kyösti Mälkki
2016-11-11
intel/sandybridge: Use common ACPI S3 recovery
Kyösti Mälkki
2016-10-29
nb/intel/sandybridge/gma: Always initialize DP buffer translation
Nico Huber
2016-10-11
nb/intel/*/graphic_init: use sizeof instead of hardcoding edid size
Arthur Heymans
2016-10-11
cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE
Nico Huber
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