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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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Age
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Author
2016-10-11
nb/intel/*/graphic_init: use sizeof instead of hardcoding edid size
Arthur Heymans
2016-10-11
cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE
Nico Huber
2016-10-04
src/northbridge: Remove unnecessary whitespace
Elyes HAOUAS
2016-10-04
src/northbridge: Remove whitespace after sizeof
Elyes HAOUAS
2016-09-27
northbridge/sandybridge/raminit_mrc.c: fix missing include
Matt DeVillier
2016-09-27
nb/intel/*/gma.c: remove spaces at the fake vbt generation
Arthur Heymans
2016-09-04
northbridge/intel/sandybridge: transition away from device_t
Antonello Dettori
2016-08-31
northbridge/intel: Add required space before opening parenthesis '('
Elyes HAOUAS
2016-08-01
Remove non-ascii & unprintable characters
Martin Roth
2016-07-31
src/northbridge: Capitalize CPU, RAM and ROM
Elyes HAOUAS
2016-07-28
bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
Furquan Shaikh
2016-07-26
intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Kyösti Mälkki
2016-07-07
intel/sandybridge: read correct leaf for cpu family
Ryan Salsamendi
2016-06-23
intel/sandybridge: Fix builds with System Agent blob
Kyösti Mälkki
2016-06-22
intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2016-06-20
nb/intel/sandybridge/raminit: Use supported CAS
Patrick Rudolph
2016-06-20
nb/intel/sandybridge/raminit: Do code cleanup
Patrick Rudolph
2016-06-20
nb/intel/sandybridge/raminit: Do code cleanup
Patrick Rudolph
2016-06-20
nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devices
Patrick Rudolph
2016-06-17
intel/model_206ax: Move platform specific defines
Kyösti Mälkki
2016-06-17
Move definitions of HIGH_MEMORY_SAVE
Kyösti Mälkki
2016-06-12
nb/intel/raminit (native): Read PCI mmio size from devicetree
Patrick Rudolph
2016-06-12
nb/intel: Factor out common MRC code
Patrick Rudolph
2016-05-31
Fix leaking CONFIG_VGA=y
Kyösti Mälkki
2016-05-04
nb/intel/sandybridge/raminit: support calling dram_freq multiple times
Patrick Rudolph
2016-05-04
nb/intel/sandybridge/raminit: add additional fallbacks
Patrick Rudolph
2016-04-29
nb/intel/sandybridge/raminit: fix regression "always use mrccache"
Patrick Rudolph
2016-04-10
nb/intel/sandybridge/raminit: always use mrccache
Patrick Rudolph
2016-04-05
nb/intel/sandybridge/raminit: die in toplevel function
Patrick Rudolph
2016-04-05
nb/intel/sandybridge/raminit: prepare raminit for fallback
Patrick Rudolph
2016-03-30
nb/intel/sandybridge/raminit: move ram training into seperate function
Patrick Rudolph
2016-03-29
nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing
Patrick Rudolph
2016-03-11
northbridge/intel: move mrccache.c of sandybridge + haswell to common
Alexander Couzens
2016-03-11
northbridge/intel: move mrc_cache definition into a common header
Alexander Couzens
2016-03-11
nortbridge/sandybridge/mrccache: parse the return code of flash->write
Alexander Couzens
2016-03-05
sandybridge/gma_lvds: support both Sandy&Ivy on one board
Iru Cai
2016-03-03
nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
Patrick Rudolph
2016-03-02
nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
Patrick Rudolph
2016-03-02
nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic
Patrick Rudolph
2016-02-28
northbridge/intel: add missing #include guards
Iru Cai
2016-02-26
nb/intel/sandybridge/raminit: Adjust timB to prevent overflow
Patrick Rudolph
2016-02-26
tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"
Denis 'GNUtoo' Carikli
2016-02-20
nb/intel/sandybridge/raminit: Add XMP support
Patrick Rudolph
2016-02-19
nb/intel/sandybridge/raminit: Improve logging
Patrick Rudolph
2016-02-18
nb/intel/sandybridge: Start PEG link training
Patrick Rudolph
2016-02-18
southbridge/intel/bd82x6x: Use common gpio.c
Patrick Rudolph
2016-02-16
nb/intel/sandybridge/raminit: Add shift offset
Patrick Rudolph
2016-02-13
sandybridge: Always include MRC if not using native RAM init.
Vladimir Serbinenko
2016-02-12
Make MRC vs native a config rather than making a separate chipset for it.
Vladimir Serbinenko
2016-02-12
Merge sandy/ivybridge romstage flow for MRC and non-MRC.
Vladimir Serbinenko
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