summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/x4x
AgeCommit message (Expand)Author
2019-01-24nb/intel/x4x: Put stage cache in TSEGArthur Heymans
2019-01-23nb/intel/x4x: Use parallel MP initArthur Heymans
2019-01-13nb/intel/x4x: Remove spurious pcidev_on_root() usageNico Huber
2019-01-10mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
2019-01-04device: Replace ugly cases of dev_find_slot()Kyösti Mälkki
2018-12-19northbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
2018-12-18northbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
2018-12-03nb/intel/x4x: Use common code for SMM in TSEGArthur Heymans
2018-11-19src: Add required space after "switch"Elyes HAOUAS
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-05nb/intel/x4x/raminit: Add missing spaceJonathan Neuschäfer
2018-10-24nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardwareArthur Heymans
2018-10-24nb/intel/*: Account for cbmem_top alignmentArthur Heymans
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-10-15nb/intel/x4x: Fix P45 CAPID max frequencyArthur Heymans
2018-10-15nb/intel/x4x: Program read training results to all ranksArthur Heymans
2018-10-08src: Use tabs for indentationElyes HAOUAS
2018-09-16nb/intel/x4x: Don't use cached settings if CPU FSB has been changedArthur Heymans
2018-09-05nb/intel/x4x/gma.c: fix skipping of native graphics initStefan Tauner
2018-08-22nb/intel/*/gma.c: Skip NGI when VGA decode is not enabledArthur Heymans
2018-08-10src: Fix typoElyes HAOUAS
2018-08-09src/northbridge: Fix typoElyes HAOUAS
2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-08-01nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 21:08:07 +0000