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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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x4x
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Commit message (
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Author
2018-11-19
src: Add required space after "switch"
Elyes HAOUAS
2018-11-16
src: Remove unneeded include <cbmem.h>
Elyes HAOUAS
2018-11-16
src: Remove unneeded include <lib.h>
Elyes HAOUAS
2018-11-16
src: Get rid of duplicated includes
Elyes HAOUAS
2018-11-12
src: Remove unneeded include "{arch,cpu}/cpu.h"
Elyes HAOUAS
2018-11-05
nb/intel/x4x/raminit: Add missing space
Jonathan Neuschäfer
2018-10-24
nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
Arthur Heymans
2018-10-24
nb/intel/*: Account for cbmem_top alignment
Arthur Heymans
2018-10-23
src: Remove unneeded whitespace
Elyes HAOUAS
2018-10-15
nb/intel/x4x: Fix P45 CAPID max frequency
Arthur Heymans
2018-10-15
nb/intel/x4x: Program read training results to all ranks
Arthur Heymans
2018-10-08
src: Use tabs for indentation
Elyes HAOUAS
2018-09-16
nb/intel/x4x: Don't use cached settings if CPU FSB has been changed
Arthur Heymans
2018-09-05
nb/intel/x4x/gma.c: fix skipping of native graphics init
Stefan Tauner
2018-08-22
nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled
Arthur Heymans
2018-08-10
src: Fix typo
Elyes HAOUAS
2018-08-09
src/northbridge: Fix typo
Elyes HAOUAS
2018-08-04
x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]
Felix Held
2018-08-01
nb/intel/x4x: Don't use PCI operations on the pci_domain device
Arthur Heymans
2018-07-30
x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]
Felix Held
2018-07-30
northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros
Felix Held
2018-06-29
sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables
Arthur Heymans
2018-06-17
nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset
Arthur Heymans
2018-06-14
nb/intel/x4x: Deprecate native graphic init
Arthur Heymans
2018-06-14
nb/intel/x4x: Fix a few things in set_enhanced_mode
Arthur Heymans
2018-06-14
nb/intel/x4x: Work around a quirk
Arthur Heymans
2018-06-14
nb/intel/x4x: Add the option for stacked channel map settings
Arthur Heymans
2018-06-08
libgfxinit: Enable G45 support (for GM45/X4X)
Nico Huber
2018-06-06
arch/x86: Make RELOCATABLE_RAMSTAGE the default
Kyösti Mälkki
2018-06-05
nb/intel/x4x: Switch to POSTCAR_STAGE
Arthur Heymans
2018-06-04
nb/intel: Use postcar_frame_add_romcache()
Nico Huber
2018-06-04
northbridge/intel: Remove unneeded includes
Elyes HAOUAS
2018-05-31
{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate
Nico Huber
2018-05-24
nb/intel/x4x: Adapt post JEDEC for DDR3
Arthur Heymans
2018-05-24
nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings
Arthur Heymans
2018-05-24
nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings
Arthur Heymans
2018-05-24
nb/intel/x4x: Implement write leveling
Arthur Heymans
2018-05-24
nb/intel/x4x: Add DDR3 JEDEC init
Arthur Heymans
2018-05-14
nb/intel/x4x/raminit: DDR3 specific ODT
Arthur Heymans
2018-05-14
nb/intel/x4x: Add DDR3 rcomp
Arthur Heymans
2018-05-14
nb/intel/x4x/raminit: Support programming initials DD3 DLL setting
Arthur Heymans
2018-05-14
nb/intel/x4x/raminit: Support programming DDR3 timings
Arthur Heymans
2018-05-14
nb/intel/x4x/raminit: Make programming launch ddr3 specific
Arthur Heymans
2018-05-14
nb/intel/x4x/raminit: Make programming crossclock support DDR3
Arthur Heymans
2018-05-14
nb/intel/x4x: Rename a things that are not specific to DDR2
Arthur Heymans
2018-05-14
nb/x4x/raminit: Decode ddr3 dimms
Arthur Heymans
2018-05-14
nb/intel/x4x/raminit: Fix programming dual channel registers
Arthur Heymans
2018-05-08
{mb,nb,soc}: Remove references to pci_bus_default_ops()
Nico Huber
2018-05-01
nb/intel/x4x: Change memory layout to improve MTRR
Arthur Heymans
2018-05-01
nb/intel/x4x: Fix programming CxDRB
Arthur Heymans
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