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path: root/src/northbridge/intel/x4x
AgeCommit message (Expand)Author
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
2018-05-01nb/intel/x4x: Fix programming CxDRBArthur Heymans
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
2018-04-30nb/x4x: Get rid of device_tElyes HAOUAS
2018-04-28nb/intel/x4x: Fix computing page_sizeArthur Heymans
2018-04-17nb/intel/x4x/rcven.c: Change the verbosity of some messagesArthur Heymans
2018-04-17nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans
2018-04-17nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans
2018-04-17nb/intel/x4x: Refactor setting default dll settingsArthur Heymans
2018-04-17nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans
2018-02-22device/ddr2,ddr3: Rename and move a few thingsArthur Heymans
2018-02-20nb/x4x/raminit_ddr2: Refactor clock configuration slightlyJonathan Neuschäfer
2018-01-05nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeoutArthur Heymans
2017-12-16nb/x4x/raminit: Rewrite SPD decode and timing selectionArthur Heymans
2017-12-12nb/intel/x4x/rcven.c: Fix programming coarse offsetArthur Heymans
2017-10-13nb/intel/*/gma: Port ACPI opregion to older platformsPatrick Rudolph
2017-09-22nb/intel/x4x: Select LAPIC_MONOTONIC_TIMERArthur Heymans
2017-08-20nb/intel/x4x: Fix booting with FSB800 DDR667 combinationArthur Heymans
2017-08-20nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans
2017-08-11nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I portsArthur Heymans
2017-08-07nb/intel/*/gma.c: Use macros for GMBUS numbersArthur Heymans
2017-07-21nb/intel/x4x: Rework programming DQ and DQS DLL timingsArthur Heymans
2017-07-21sb/intel/i82801jx: Add correct PCI ids and change namesArthur Heymans
2017-06-04Kconfig: Add choice of framebuffer modeNico Huber
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
2017-06-02Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFGNico Huber
2017-05-24nb/intel/x4x/raminit: Initialise async variableArthur Heymans
2017-05-22nb/intel/x4x: Use a struct for dll settings instead of an arrayArthur Heymans
2017-05-21nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUPArthur Heymans
2017-05-20nb/intel/x4x/raminit: Remove very long delayArthur Heymans
2017-05-13nb/intel/x4x: Fix uninitialized variable issueNico Huber
2017-05-11nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESSArthur Heymans
2017-05-10nb/intel/x4x: Add support for second PEG slotArthur Heymans
2017-05-09nb/x4x: Do not enable IGD when not supportedArthur Heymans
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