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path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2020-03-23nb/intel/sandybridge: Use cached CPUIDAngel Pons
2020-03-23nb/intel/sandybridge: Void MRC cache if CPUID differsAngel Pons
2020-03-23nb/intel/sandybridge: Store CPUID in ctrl structAngel Pons
2020-03-23nb/intel/sandybridge: Add warning to saved structsAngel Pons
2020-03-23nb/intel/sandybridge: Remove unnecessary declarationAngel Pons
2020-03-23nb/intel/sandybridge: Do not define tables in a headerAngel Pons
2020-03-23nb/intel/sandybridge: Reflow raminit tablesAngel Pons
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
2020-03-23nb/intel/sandybridge: Remove oddball `- 1` in tRFCAngel Pons
2020-03-22nb/intel/sandybridge: Drop spurious register writeAngel Pons
2020-03-20nb/intel/sandybridge: Deduplicate report_memory_configAngel Pons
2020-03-20nb/intel/sandybridge: Always write to PEGCTLAngel Pons
2020-03-19nb/intel/sandybridge: Use loops on DMI register groupsAngel Pons
2020-03-18nb/intel/sandybridge: Tidy up code and commentsAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-03-16nb/intel/i945/raminit: Simplify if conditionPaul Menzel
2020-03-15nb/intel/pineview: Clean up code and commentsAngel Pons
2020-03-15treewide: Replace uses of "Nehalem"Angel Pons
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
2020-03-15nb/intel/i945/raminit: Use boolean type for helper variablesPaul Menzel
2020-03-15nb/intel/i945/raminit: Remove space for correct alignmentPaul Menzel
2020-03-15nb/intel/haswell: Tidy up code and commentsAngel Pons
2020-03-11intel/i945: Call fixup_i945_errata() only for mobile versionElyes HAOUAS
2020-03-07src/nb: Use 'print("%s...", __func__)'Elyes HAOUAS
2020-03-06northbridge: Remove unused include <device/pci.h>Elyes HAOUAS
2020-03-06nb/intel/haswell/peg: Add PEG driver stubChris Morgan
2020-03-04nb/intel/nehalem: Use cache.h functionsArthur Heymans
2020-03-02nb/intel/sandybridge: Fix VBOOTPatrick Rudolph
2020-02-24treewide: Capitalize 'CMOS'Elyes HAOUAS
2020-02-24src: capitalize 'RAM'Elyes HAOUAS
2020-02-21nb/intel/snb: Add PCI routing table for PEG root portsJames Ye
2020-02-18nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI IDJonathan A. Kollasch
2020-02-18nb/intel/sandybridge: use list of northbridge device IDsJonathan A. Kollasch
2020-02-17nb/intel/gm45: Fix typo in console messageElyes HAOUAS
2020-02-17nb/intel/nehalem: Remove unused MRC_CACHE_SIZEElyes HAOUAS
2020-02-12nb/intel/sandybridge/acpi: Fix MMCONF size computationPatrick Rudolph
2020-02-12nb/intel/sandybridge/acpi: Update PEG codePatrick Rudolph
2020-02-06nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)Chris Morgan
2020-02-01nb/intel/sandybridge: improve indexed register helper macrosFelix Held
2020-01-29nb/intel/i945: Use boot path macrosPaul Menzel
2020-01-27nb/intel/sandybridge/raminit_common.h: add missing stdint.h includeFelix Held
2020-01-27nb/intel/sandybridge: replace NORTHBRIDGE with HOST_BRIDGE defineFelix Held
2020-01-26intel/i440bx: Resolve long standing raminit TODOsKeith Hui
2020-01-26intel/i440bx: Add timestamp to RAM initKeith Hui
2020-01-26intel/i440bx: Use smbus_read_byte() for raminit debugKeith Hui
2020-01-16nb/intel/sandybridge: sort LANEBASE_* defines by their addressFelix Held
2020-01-16nb/intel/sandybridge: add macros for byte lane register offsetsFelix Held
2020-01-16nb/intel/sandybridge: refactor code around lane_base[]Felix Held
2020-01-15nb/intel/sandybridge: refactor lane_registers[]Felix Held
2020-01-15nb/intel/sandybridge: drop LyCx(r, x, y) macroFelix Held
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