summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2012-11-02Fix some issues with new "reference" toolchainStefan Reinauer
2012-10-26northbridge/sch: move the \n so it reads a little betterSebastian Andrzej Siewior
2012-10-26northbridge/sch: read the size of main memory from the proper registerSebastian Andrzej Siewior
2012-10-26northbridge/sch: Read the GPU memory from the correct PCI deviceSebastian Andrzej Siewior
2012-10-26northbridge/sch: don't overwrite hightables with GPU / TSEG memorySebastian Andrzej Siewior
2012-10-07Remove chip.h files without config structureKyösti Mälkki
2012-09-25HAVE_HIGH_TABLES is gonePatrick Georgi
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2012-08-09Sandybridge: Fix integer overrun in romstage udelay()Stefan Reinauer
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
2012-08-07Sandy/Ivy Bridge and Cougar/Panther Point: Fix namesStefan Reinauer
2012-08-01Intel and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
2012-08-01Intel Sandybridge and UMA: use mmio_resource()Kyösti Mälkki
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
2012-07-30sandybridge: reinitialize usbdebug after MRCSven Schnelle
2012-07-27Intel and GFXUMA: fix MTRR and use uma_resource()Kyösti Mälkki
2012-07-27Intel 82810 and 82830: always room for PCI memoryKyösti Mälkki
2012-07-27Intel i945 and sch: no memory over 4GBKyösti Mälkki
2012-07-26Refactor driver structsPatrick Georgi
2012-07-26CTDP: Only do TDP down/nominal change from TNP0Duncan Laurie
2012-07-26ACPI: Add support for runtime config TDP downDuncan Laurie
2012-07-25ELOG: Add support for a monotonic boot counter in CMOSDuncan Laurie
2012-07-25More descriptive error messages in Sandybridge raminit codeStefan Reinauer
2012-07-24ELOG: Fix boot count increment for non-wake caseDuncan Laurie
2012-07-24Ivybridge: fix workaround and enable PAIRDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24Make ACPI code detect Sandy/Ivy Bridge dynamicallyStefan Reinauer
2012-07-24Drop (empty) sandybridge_late_initialization()Stefan Reinauer
2012-07-24Add support for HM70 and NM70 LPC bridgeStefan Reinauer
2012-07-24Print PCI ID of PCH during boot upStefan Reinauer
2012-07-24Drop leading spaces from CPU name stringStefan Reinauer
2012-07-24Fix MRC cache update delaysStefan Reinauer
2012-07-24SandyBridge: Add another PCI device ID for northbridgeWalter Murphy
2012-07-24Fixes to enable RC6 on IvyBridgeDuncan Laurie
2012-07-22i945: Disable IGD if plugin VGA is preferredPatrick Georgi
2012-07-20Fix udelay() implementation for i945 romstageNico Huber
2012-07-20Intel SCH northbridge: fix resource indexKyösti Mälkki
2012-07-16Define global uma_memory variablesKyösti Mälkki
2012-07-16i5000: Fix resource allocationSven Schnelle
2012-07-09i5000: reset system if raminit failsSven Schnelle
2012-07-06i5000: Add PCI ids for all i5000 flavoursSven Schnelle
2012-07-06i945: Reset IGD on bootPatrick Georgi
2012-06-20i5000: fix another typoSven Schnelle
2012-06-20i5000: fix typosSven Schnelle
2012-06-18i5000: enforce hard resetSven Schnelle
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
2012-05-11Hook up MRC cache updateStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 18:20:13 +0000