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path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2015-11-24northbridge/intel/pineview: Add minimal Pineview northbridgeDamien Zammit
2015-11-19nb/intel/sandybridge/raminit: Factor out code into toggle_io_resetPatrick Rudolph
2015-11-19nb/intel/sandybridge/raminit: Comment the codePatrick Rudolph
2015-11-18nb/intel/sandybridge: Fix PEG disablementPatrick Rudolph
2015-11-18nb/intel/sandybridge/northbridge: Initialize uma_memory_base in all casesPatrick Rudolph
2015-11-18northbridge/intel/sandybridge: Fix random raminit failuresPatrick Rudolph
2015-11-17northbridge/intel/fsp_sandybridge: remove blank lineMartin Roth
2015-11-10northbridge/intel: Add i89xx header fileMarc Jones
2015-11-05nb/intel/sandybridge: Limit GFX workaround to Sandy BridgeNico Huber
2015-11-04nb/intel/sandybridge: Add ACPI DMAR tableNico Huber
2015-11-04nb/intel/sandybridge: Enable basic IOMMU supportNico Huber
2015-11-04ACPI: Make DMAR flags settableNico Huber
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-30Drop northbridge/i440lxStefan Reinauer
2015-10-29nb/intel/sandybridge/gma: add disable functionPatrick Rudolph
2015-10-23Intel: Move MCRS ResourceTemplate outside of _CRS methodMartin Roth
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
2015-10-12gma: Consolidate Intel IGD ACPI code some moreNico Huber
2015-10-11Kill lvds_num_lanesVladimir Serbinenko
2015-10-11Derive lvds_dual_channel from EDID timings.Vladimir Serbinenko
2015-10-09nb/intel/sandybridge/raminit: Add edge write discovery checkPatrick Rudolph
2015-10-09northbridge/intel/sandybridge: Do not disable PEG by defaultPatrick Rudolph
2015-10-09northbridge/intel/sandybridge: Enable PEG clock-gating on demandPatrick Rudolph
2015-10-04northbridge/intel/nehalem: Fix native VGA initNicolas Reinecke
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-10-01northbridge/intel/gm45: Fix native VGA initAudrey Pearson
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
2015-09-07intel/sandybridge: Do not guard native VGA init by #ifdefsAlexandru Gagniuc
2015-09-07intel i945: Fix native VGA initializationMono
2015-09-07north/intel/sandybridge: Fix native VGA initializationAlexandru Gagniuc
2015-09-07intel: Do not hardcode the position of mrc.cacheAlexandru Gagniuc
2015-09-04bootstate: remove need for #ifdef ENV_RAMSTAGEAaron Durbin
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-08-31northbridge/intel/gm45/Kconfig: Remove IOMMU symbol choiceMartin Roth
2015-08-28edid: Use edid_mode struct to reduce redundancyDavid Hendricks
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
2015-08-10intel/i945: don't read structs out of uninitialized pointersPatrick Georgi
2015-07-29intel/haswell: fix CHROMEOS builds for haswellPatrick Georgi
2015-07-22intel raminit: rewrite timB high adjust calculationPatrick Rudolph
2015-07-22intel raminit: support two DIMMs per channelPatrick Rudolph
2015-07-17Remove unused Kconfig symbols in c codeMartin Roth
2015-07-14intel/sandybridge/gma: Add graphics PCI Device IDs 0x0162 and 0x0152Damien Zammit
2015-07-13x86: flatten hierarchyStefan Reinauer
2015-07-13intel raminit: improve loggingPatrick Rudolph
2015-07-13intel raminit: fix timB high adjust calculationPatrick Rudolph
2015-07-13intel raminit: whitespace fixesPatrick Rudolph
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