coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-11-12	Initial IGD OpRegion implementation	Stefan Reinauer
2012-11-12	Avoid using hardcoded values in MRC cache code	Vadim Bendebury
2012-11-09	Make coreboot use the offset parameter in cbfstool create	Stefan Reinauer
2012-11-09	Make register/value lists const	Stefan Reinauer
2012-11-07	SandyBridge/IvyBridge: Use flash map to find MRC cache	Stefan Reinauer
2012-11-07	Add missing newline in error message	Stefan Reinauer
2012-11-07	CMOS: Move MRC seed offset into upper bank	Duncan Laurie
2012-11-02	Fix some issues with new "reference" toolchain	Stefan Reinauer
2012-10-26	northbridge/sch: move the \n so it reads a little better	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: read the size of main memory from the proper register	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: Read the GPU memory from the correct PCI device	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: don't overwrite hightables with GPU / TSEG memory	Sebastian Andrzej Siewior
2012-10-07	Remove chip.h files without config structure	Kyösti Mälkki
2012-09-25	HAVE_HIGH_TABLES is gone	Patrick Georgi
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2012-08-09	Sandybridge: Fix integer overrun in romstage udelay()	Stefan Reinauer
2012-08-08	Cleanup coreboot memory table includes	Kyösti Mälkki
2012-08-07	Sandy/Ivy Bridge and Cougar/Panther Point: Fix names	Stefan Reinauer
2012-08-01	Intel and GFXUMA: drop redundant use of lb_add_memory_range()	Kyösti Mälkki
2012-08-01	Intel Sandybridge and UMA: use mmio_resource()	Kyösti Mälkki
2012-08-01	Intel Sandybridge: add reserved memory as resources	Kyösti Mälkki
2012-07-30	sandybridge: reinitialize usbdebug after MRC	Sven Schnelle
2012-07-27	Intel and GFXUMA: fix MTRR and use uma_resource()	Kyösti Mälkki
2012-07-27	Intel 82810 and 82830: always room for PCI memory	Kyösti Mälkki
2012-07-27	Intel i945 and sch: no memory over 4GB	Kyösti Mälkki
2012-07-26	Refactor driver structs	Patrick Georgi
2012-07-26	CTDP: Only do TDP down/nominal change from TNP0	Duncan Laurie
2012-07-26	ACPI: Add support for runtime config TDP down	Duncan Laurie
2012-07-25	ELOG: Add support for a monotonic boot counter in CMOS	Duncan Laurie
2012-07-25	More descriptive error messages in Sandybridge raminit code	Stefan Reinauer
2012-07-24	ELOG: Fix boot count increment for non-wake case	Duncan Laurie
2012-07-24	Ivybridge: fix workaround and enable PAIR	Duncan Laurie
2012-07-24	CPU: Add basic support for Nominal Configurable TDP	Duncan Laurie
2012-07-24	Rename cache_lbmem() to cache_ramstage()	Stefan Reinauer
2012-07-24	Make ACPI code detect Sandy/Ivy Bridge dynamically	Stefan Reinauer
2012-07-24	Drop (empty) sandybridge_late_initialization()	Stefan Reinauer
2012-07-24	Add support for HM70 and NM70 LPC bridge	Stefan Reinauer
2012-07-24	Print PCI ID of PCH during boot up	Stefan Reinauer
2012-07-24	Drop leading spaces from CPU name string	Stefan Reinauer
2012-07-24	Fix MRC cache update delays	Stefan Reinauer
2012-07-24	SandyBridge: Add another PCI device ID for northbridge	Walter Murphy
2012-07-24	Fixes to enable RC6 on IvyBridge	Duncan Laurie
2012-07-22	i945: Disable IGD if plugin VGA is preferred	Patrick Georgi
2012-07-20	Fix udelay() implementation for i945 romstage	Nico Huber
2012-07-20	Intel SCH northbridge: fix resource index	Kyösti Mälkki
2012-07-16	Define global uma_memory variables	Kyösti Mälkki
2012-07-16	i5000: Fix resource allocation	Sven Schnelle
2012-07-09	i5000: reset system if raminit fails	Sven Schnelle
2012-07-06	i5000: Add PCI ids for all i5000 flavours	Sven Schnelle
2012-07-06	i945: Reset IGD on boot	Patrick Georgi