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path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
2013-02-11spi.h: Rename the spi.h to spi-generic.hZheng Bao
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
2013-01-14Support for Celeron 1007UStefan Reinauer
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
2012-11-27Drop driver-y from GM45/ICH9/RK9Stefan Reinauer
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
2012-11-27Get rid of drivers classPatrick Georgi
2012-11-27intel/gm45: new northbridgePatrick Georgi
2012-11-24yabel: Use X86_* instead of the more verbose M.x86.REG_*Patrick Georgi
2012-11-17Use new system agent binariesStefan Reinauer
2012-11-14Sandybridge: Set PEG clock gatingMarc Jones
2012-11-14Add PCIe init and NMode flag to PEI data structureStefan Reinauer
2012-11-14Add ddr3lv_support flag to pei_data structureDuncan Laurie
2012-11-14pei_data.h: Fix commentMarc Jones
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
2012-11-12Initial IGD OpRegion implementationStefan Reinauer
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
2012-11-09Make coreboot use the offset parameter in cbfstool createStefan Reinauer
2012-11-09Make register/value lists constStefan Reinauer
2012-11-07SandyBridge/IvyBridge: Use flash map to find MRC cacheStefan Reinauer
2012-11-07Add missing newline in error messageStefan Reinauer
2012-11-07CMOS: Move MRC seed offset into upper bankDuncan Laurie
2012-11-02Fix some issues with new "reference" toolchainStefan Reinauer
2012-10-26northbridge/sch: move the \n so it reads a little betterSebastian Andrzej Siewior
2012-10-26northbridge/sch: read the size of main memory from the proper registerSebastian Andrzej Siewior
2012-10-26northbridge/sch: Read the GPU memory from the correct PCI deviceSebastian Andrzej Siewior
2012-10-26northbridge/sch: don't overwrite hightables with GPU / TSEG memorySebastian Andrzej Siewior
2012-10-07Remove chip.h files without config structureKyösti Mälkki
2012-09-25HAVE_HIGH_TABLES is gonePatrick Georgi
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2012-08-09Sandybridge: Fix integer overrun in romstage udelay()Stefan Reinauer
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
2012-08-07Sandy/Ivy Bridge and Cougar/Panther Point: Fix namesStefan Reinauer
2012-08-01Intel and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
2012-08-01Intel Sandybridge and UMA: use mmio_resource()Kyösti Mälkki
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
2012-07-30sandybridge: reinitialize usbdebug after MRCSven Schnelle
2012-07-27Intel and GFXUMA: fix MTRR and use uma_resource()Kyösti Mälkki
2012-07-27Intel 82810 and 82830: always room for PCI memoryKyösti Mälkki
2012-07-27Intel i945 and sch: no memory over 4GBKyösti Mälkki
2012-07-26Refactor driver structsPatrick Georgi
2012-07-26CTDP: Only do TDP down/nominal change from TNP0Duncan Laurie
2012-07-26ACPI: Add support for runtime config TDP downDuncan Laurie
2012-07-25ELOG: Add support for a monotonic boot counter in CMOSDuncan Laurie
2012-07-25More descriptive error messages in Sandybridge raminit codeStefan Reinauer
2012-07-24ELOG: Fix boot count increment for non-wake caseDuncan Laurie
2012-07-24Ivybridge: fix workaround and enable PAIRDuncan Laurie