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2014-09-25peppy and falco: set panel power timings in northbridge, using devicetree, ↵Ronald G. Minnich
not mainboards Historically we had set panel timing in the mainboard gma code. This goes back to the replay-attack video startup. We can let the haswell gma code set these values from the device tree settings. Change-Id: If32150d2857241ca2d2c88880086f49d25815d76 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/180521 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 406eab3ca6a9bc59382866817786bf96bbb19d56) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6911 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-24northbridge/intel/i945/Kconfig: Select VGAPaul Menzel
Commit 0092c999 (i945: Support text mode gfx init) [1] broke building the Lenovo X60 with native graphics initialization by selecting `CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT`. CC northbridge/intel/i945/gma.ramstage.o src/northbridge/intel/i945/gma.c: In function 'intel_gma_init': src/northbridge/intel/i945/gma.c:398:2: error: implicit declaration of function 'vga_textmode_init' [-Werror=implicit-function-declaration] Selecting the Kconfig variable VGA makes the declaration of the function `vga_textmode_init()` to be included by the preprocessor. [1] http://review.coreboot.org/6723 Change-Id: Iecbb2898193078b8738425cea13cb7e6da508cab Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6947 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-09-22haswell: Move to per-device ACPIVladimir Serbinenko
Change-Id: Ic724dcf516d9cb78e89698da603151a32d24e978 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6814 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-13intel/gma: consolidate vbt codeVladimir Serbinenko
Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6800 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-11Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko
Change-Id: I3d664ab575bf9c49a7bff9a395fbab96748430d0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6802 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-09-08Haswell/falco/peppy/slippy: continue to clean up FUI.Ronald G. Minnich
As a first step towards removing hardcodes from the FUI support, change the haswell call to i915_lightup to panel_lightup, and pass the intel_dp * as a parameter. Get rid of the scalar arguments and make them part of intel_dp. Get rid of file-scope variables and use the ones in the intel_dp struct. In falco, use functions that peppy uses. Drop slippy support for FUI, it's a dead board; if this is ok I'll remove the files next. And, incidentally, fix the broken RGBX constant and change it to BGRX. Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/174932 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6833 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-30AMD Steppe Eagle: Add northbridge files for new SoC familyBruce Griffith
Add the northbridge file for AMD's new Mullins and Steppe Eagle processor family. Since the processor family name is not the same across AMD's sales and marketing channels, I have elected to use part of the processor ID as the family name. The intent is to reduce confusion since the processor ID is the same for both families. This northbridge support has only been validated on the AMD Embedded variants ("Steppe Eagle"). The AGESA wrappers in coreboot have a function that is intended to mirror the UMA memory allocation performed during memory initialization by AGESA. Update the Steppe Eagle memory allocation to mimic the memory reservation done inside the AGESA BLOB. Change the default CBMEM address, the default video BIOS device ID, and a couple of other defaults to match changes in coreboot community code. The northbridge chip.h specifies how many processor sockets, how many channels, and how many DIMM slots are supported by the northbridge. Steppe Eagle does not permit multisocket systems and has only one memory controller channel. Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6678 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30sandybridge: Add native sandybridgeVladimir Serbinenko
Change-Id: I1b51310b4387e588c4828563620b0e2770598503 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6753 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-26Peppy, Haswell: refactor and create set_translation_table function in ↵Ronald G. Minnich
haswell/gma.c The code to set the graphics translation table has been in the mainboards, but should be in the northbridge support code. Move the function, give it a better name, and enable support for > 4 GiB while we're at it, in the remote possibility that we get some 8 GiB haswell boards. Change-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/171160 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit d5a429498147c479eb51477927e146de809effce) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6741 Tested-by: build bot (Jenkins)
2014-08-25intel/gma: Clarify code and use dedicated init for Google PeppyRonald G. Minnich
Peppy had some issues with FUI. We decided it was time to create peppy-specific gma.c and i915io.c files. Using yabel and the i915tool, we generated a replay attack, then interpolated against the slippy i915io.c to get something working. Also, in preparation for moving code out of the mainboard gma.c to generic driver code, we got rid of some hardcodes in the mainboard gma.c that have no business being there. The worst were the computation of gmch_[m,n] and it turns out that we had some long-standing bugs related to confusion about 'bpp'. I've killed the word bpp everywhere I could because there are at least 3 things that correspond to bpp. We now have framebuffer, pipe, and panel bpp. The names are long because I want to avoid all the mistakes we've all been making in the last year :-) Sadly, that means a lot of changes not just peppy-related, but they are simple and in a good cause. The test pattern generation is driven by a global variable in mainboard/peppy/gma.c. I've found in the past that it's very useful to have a function like this available, as one can activate it while using a jtag debugger: halt at the right place in ramstage, set the variable to 1, continue. It's not enough code to worry about always including. The last hard-codes for M and N registers are gone, and the function to set from generic intel_dp.c code works. To avoid screen trash on a dev mode boot, which we liked but nobody else did :-), we now take the time to put a pleasing background color that sort of doubles as a power LED. Rough timing is ramstage start is at 2.2, and dev setup is done at 3.3. These new platforms are depressingly slow to boot. Rom init alone is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash prompt. These CPUs are at least 10x faster and take much longer to get going. Future work, once we get this through, is to move more functions to the intel driver, and combine the mainboard i915io.c into the mainboard gma.c. That separation only existed because i915io.c was generated by a tool, and it had lots of ugliness. Most ugliness is gone. Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/170013 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> (cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d) snow: Fix a typo in devicetree.cb that was breaking the snow build. A typo in a recent change broke the snow build. Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171014 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 154876c126a6690930141df178485658533096d2) Squashed a fix into the initial patch and updated nehalem/gma.c to have a non-static gtt_poll. Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6657 Tested-by: build bot (Jenkins)
2014-08-25sandybridge: Show spew raminit messages only with raminit debugVladimir Serbinenko
Change-Id: Ifbc59c28c8d8bd844801da9cb869c5dfbda09168 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6754 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-25sandybridge: Native gfx init.Vladimir Serbinenko
Change-Id: I07590086ffe3b1d068fa6ae6b156039cc2e55893 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6755 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-22lenovo/x200: Move video ASL code to northbridge.Vladimir Serbinenko
Change-Id: I58760500252e78da947685c18201b6d446368333 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6729 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21Merge LCD on nehalemVladimir Serbinenko
Change-Id: I09852ea56495da17e7607064d74d98f2296f34b1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6721 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21Merge LCD on sandy/ivyVladimir Serbinenko
Change-Id: Ibf66d46f47fe465cc805f85de818a77327cd7258 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6722 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945: Support text mode gfx initVladimir Serbinenko
Change-Id: I952fdb113e2696785695b416d9292b7107099994 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6723 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945/gma: don't map the page tableVladimir Serbinenko
Change-Id: I20fb5323cde1f83a3d3adc98251b2f31de25ed24 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945: Remove GTT avoidance offset.Vladimir Serbinenko
Not needed anymore with GTT at the end of range. Change-Id: I57b02c7d605d3c43ac92bd744bb6472e3c3471e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6717 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-20intel/i945/gma: Place GTT below top of memoryPaul Menzel
Since commit 17fec8a0 [1] drm/i915: Use Graphics Base of Stolen Memory on all gen3+ present in the Linux kernel since version 3.12, 3D does not work anymore [2]. Comparing the graphics registers, in this case that means output of `intel_reg_dumper`, the vendor Video BIOS is setting the register PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to `0x3ffc0001` on a system with 1 GB of RAM, while native graphics init sets it to `0x3f800001`. Currently native graphis init sets the GTT right above the base address of stolen memory. The Video BIOS sets it below the top of memory. The Linux Intel driver expects it to be below top of memory, so do it this way, by setting the address to TOM minus the size of the GTT, which is hardcoded to 256 KiB. As `PGETBL_CTL` is zero by default, reading its value in the beginning is not necessary and is only confusing. Make it clear that the code calculates the value. There is still a PTE error reported during boot, but 3D works with Linux 3.12+ and no user visible problems are shown. [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=17fec8a08698bcab98788e1e89f5b8e7502ababd [2] https://bugs.freedesktop.org/show_bug.cgi?id=79038 [3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_1_graphics_core_0.pdf Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller Programmer’s Reference Manual Volume 1: Graphics Core Revision 1.0a Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/5927 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-17gm45: Declare BIOS memory as RAM.Vladimir Serbinenko
So it's in line with other boards and those addresses are cached for faster access. Change-Id: I7794d75ef1e3ceea6b2a4acba01e4af5d1f005f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6689 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-17i945: Replace video gfx init.Vladimir Serbinenko
Old init was a replay not even meant to have been committed. This one really computes values and does its job. Tested on Macbook2,1 (1280x800) and X60 (1024x768). Change-Id: I61b6946c095fe06e20ae9a0db54696d0568225dd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5320 Reviewed-by: Francis Rowe <info@gluglug.org.uk> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16AMD Family 14: Fix permissions on one northbridge fileBruce Griffith
fam14_callouts.h should not have the execute bit set. Change-Id: Iab44d04f2c9669e28d2d5028b0a11e565cc7bb07 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6675 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Decrease MTRR usageVladimir Serbinenko
Change-Id: I4c790b0eaf2af94286e6691281fcad3d14659a99 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6687 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Make UMA size configurable.Vladimir Serbinenko
Change-Id: I27b2ec70b9c77f3caf9d52788f46f5dc16045d1b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6686 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Recognize 48MiB gfx UMA.Vladimir Serbinenko
Change-Id: I33e6b357ea044d6ec00b119e84cbada7bf58317f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6685 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16intel/gm45: native gfx init.Vladimir Serbinenko
Tested on lenovo X200 in both text and gfx mode. Change-Id: I273971d0f34ca3529959d4228e9516775459b806 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6682 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-14gm45: Set acpi_slp_type only once.Vladimir Serbinenko
It doesn't harm to set several times but it pollutes the log. Change-Id: I7aad7f0229a7d9d071ba844a1cfa123dffc4cacf Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6653 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-08-13Falco/Slippy: Patch to refactor haswell/gma.c and ↵Furquan Shaikh
mainboard/google/slippy/i915io.c A large portion of documented registers have been initialized using macros. Only a few undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant calls. However, some more work is required to correctly identify which calls are not required. All the io_writes are replaced by gtt_writes. Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66204 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6600 Tested-by: build bot (Jenkins)
2014-08-13gm45: Allow skiping voltage config.Vladimir Serbinenko
Change-Id: I81b9966212d09d4d2561b3adc20d6d8a8a200f4b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6630 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12gm45: Move S3 detection to enable stage.Vladimir Serbinenko
Also move it to NB to be in line with other. Change-Id: Ibd961d60dcd686899f34f6a494c14ff9d65e618b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12gm45: Reserve RAM for ME if it's active.Vladimir Serbinenko
Change-Id: Icd2b075cec9461f9d6028a8c845f6900b6fe04c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6628 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12gm45: Allow coexistance with ME firmware.Vladimir Serbinenko
Change-Id: I08ca5eec94c70b43789122266d68af149772385c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12gm45: Ensure that brightness register in gma contains sane value.Vladimir Serbinenko
Change-Id: Ia66c71c3adf2ae0d413750b5e59e3eaba3888a0b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6587 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-11gm45: Declare brightness variables for ACPI use.Vladimir Serbinenko
Change-Id: I23a088919aaac16066e5dd8300a081a8095a93f0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6589 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-11northbridge/intel/*/gma.c: Remove dead codeEdward O'Callaghan
Remove some dead coded spotted in Clang builds. Change-Id: Ia23e16eae76593eee249e0894ef1d704a274616f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6130 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-08-11gm45: Set default VGA PCIID.Vladimir Serbinenko
Change-Id: I2eba1ca27c1f8181a9c6288f6794922915575790 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6586 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10Falco/Slippy: Patch to remove redundant graphics initializationsFurquan Shaikh
gma_fui_init repeats the initializations already performed in gma_setup_panel. These redundant initializations reset any gtt settings done before this call. Hence, they had to be done again after call to gma_fui_init. However, the call gma_fui_init is not required at all. Does not affect the behavior of suspend/resume. Old-Change-Id: Idfb9f9930624694b878ddc0fe8648b3c8dd80e55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65997 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit c376aea1b89c9a829874d5c657693993a3bb1f13) Falco/Slippy: Patch to fix garbage on screen during graphics initialization in normal mode Depending on the init_fb parameter: 1) For normal mode, first page is filled with zeroes and setgtt is used make all GTT entries point to this same page 2) For developer/recovery mode, we init the gtt to consecutive pages Old-Change-Id: I281b0b7efe01f7892e98b19ff9a63c04b087bd2c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 97c99dfe52ef3a87d387fdbf27ad3a28ad81c722) Squashed two graphics related commits for Falco/Slippy. Change-Id: I7ddb92672c026fe66f9fb0caba9d8fdc3f8a9d0a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6536 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-09ivybridge: Don't propose to include systemagent on native boards.Vladimir Serbinenko
Change-Id: Ib70a6741b55609840b6fd2fca16bcf9883bf143c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6566 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-08-05northbridge/via/vx800: Fix out-of-bounds read due to off-by-oneEdward O'Callaghan
Change-Id: Ia7fda59b60b2148dd4d246686bd94d2334b23eb5 Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6485 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-04northbridge/intel: Out of bounds write to array in gma.hEdward O'Callaghan
The signature[] array in the mailbox struct opregion_header_t has IGD_OPREGION_SIGNATURE written to it with a sizeof(IGD_OPREGION_SIGNATURE) and not a sizeof(signature[]). This resulted in a silent off-by-one out of bounds illegal write. Change-Id: I651620a753c743dd2ed2af51c012c27c14a5ea25 Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-03nehalem: Make UMA size configurable in CMOS.Vladimir Serbinenko
All modes tested on X201. Change-Id: I23df81523196ea3f5fdb10eb04f4496c00aaeb9f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-03sandy/ivybridge: Make UMA size configurable.Vladimir Serbinenko
Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6470 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-31northbridge/amd/agesa/agesawrapper_call.h: Decode status codesEdward O'Callaghan
Decode obscure AGESA status codes into their respective string forms. Change-Id: Iccf175ef62e5005af6ebbfb1bd0acec8aedc2eaa Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6402 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-07-30northbridge/intel: Add fsp_rangeley northbridge supportMartin Roth
This adds the northbridge initialization pieces for Intel's Atom C2000 processor (Formerly Rangeley). It is intended to be used with the Intel Atom C2000 FSP and does not contain all of the pieces that would otherwise be required for initialization. Not currently supported: S3 suspend/resume CAR memory Migration (No early cbmem console) SMM Change-Id: I7665212c892d9a08ecf35d7be70d0afe5fd2c77b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6369 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29gm45: Move spd address map to board-specific config.Vladimir Serbinenko
Change-Id: I8f45a821ecd414dbd0129ae6d583d4e7dc06bc5a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5931 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-07-29northbridge/intel/sandybridge/raminit_native: Remove stale FIXME.Vladimir Serbinenko
S3 works just fine. Change-Id: Icd7ae5ad8941bf749a4450efc61e7cede52bf5ef Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6407 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6384 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29northbridge/intel/nehalem/northbridge.c: Remove unused variableEdward O'Callaghan
Spotted by Clang. Change-Id: I17e64ee989b611fac91072b9e97eab168cfae525 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6128 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-07-29x230: Deploy VBTVladimir Serbinenko
Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5396 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-07-29nehalem: Remove fake_vbt copying.Vladimir Serbinenko
Instead generate simple VBT in code. Tested on X201. Change-Id: I2244053edd24c22694161d9bf5f7f2f3eb4e2f57 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5895 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 07:30:04 +0000