index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
northbridge
Age
Commit message (
Expand
)
Author
2016-03-30
nb/intel/sandybridge/raminit: move ram training into seperate function
Patrick Rudolph
2016-03-29
nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing
Patrick Rudolph
2016-03-28
nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()
Timothy Pearson
2016-03-26
nb/amd/amdmct: Select max_lanes based on ECC presence or absence
Damien Zammit
2016-03-24
nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
Timothy Pearson
2016-03-23
nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_...
Timothy Pearson
2016-03-21
nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
Timothy Pearson
2016-03-16
cpu/x86/mtrr: move cache_ramstage() to its only user
Aaron Durbin
2016-03-13
nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
Timothy Pearson
2016-03-13
northbridge/intel/i3100: Unify UDELAY selection
Stefan Reinauer
2016-03-13
northbridge/intel/i82810: Unify UDELAY selection
Stefan Reinauer
2016-03-12
northbridge/intel/i82830: Unify UDELAY selection
Stefan Reinauer
2016-03-12
nb/amd/mct_ddr3: Consolidate duplicated code
Timothy Pearson
2016-03-11
northbridge/intel: move mrccache.c of sandybridge + haswell to common
Alexander Couzens
2016-03-11
northbridge/intel: move mrc_cache definition into a common header
Alexander Couzens
2016-03-11
nortbridge/sandybridge/mrccache: parse the return code of flash->write
Alexander Couzens
2016-03-11
nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Require minumum training quality for both read and write
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
Timothy Pearson
2016-03-11
northbridge/i945/gma: Re-enable NVRAM tft_brightness
Alexander Couzens
2016-03-10
northbridge/intel/i440bx: Unify UDELAY selection
Stefan Reinauer
2016-03-09
northbridge/intel/gm45: Use TSC for ramstage timer per default
Stefan Reinauer
2016-03-05
sandybridge/gma_lvds: support both Sandy&Ivy on one board
Iru Cai
2016-03-03
nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
Patrick Rudolph
2016-03-02
nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
Patrick Rudolph
2016-03-02
nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic
Patrick Rudolph
2016-02-28
northbridge/intel: add missing #include guards
Iru Cai
2016-02-26
nb/intel/sandybridge/raminit: Adjust timB to prevent overflow
Patrick Rudolph
2016-02-26
tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"
Denis 'GNUtoo' Carikli
2016-02-20
nb/intel/sandybridge/raminit: Add XMP support
Patrick Rudolph
2016-02-19
nb/amd/amdmct: Add socket specific configuration for FM2
Damien Zammit
2016-02-19
nb/intel/sandybridge/raminit: Improve logging
Patrick Rudolph
2016-02-18
nb/intel/sandybridge: Start PEG link training
Patrick Rudolph
2016-02-18
southbridge/intel/bd82x6x: Use common gpio.c
Patrick Rudolph
2016-02-16
nb/intel/sandybridge/raminit: Add shift offset
Patrick Rudolph
2016-02-13
sandybridge: Always include MRC if not using native RAM init.
Vladimir Serbinenko
2016-02-12
Make MRC vs native a config rather than making a separate chipset for it.
Vladimir Serbinenko
2016-02-12
Merge sandy/ivybridge romstage flow for MRC and non-MRC.
Vladimir Serbinenko
2016-02-10
Kconfig: Move defaults for CBFS_SIZE
Martin Roth
2016-02-09
sandybridge: Set all native gfx-related options in northbridge code.
Vladimir Serbinenko
2016-02-09
ivy: Add a possiblity for mainboard early init.
Vladimir Serbinenko
2016-02-09
Revert "northbridge/intel/peg: Disable unused ports"
Nico Huber
2016-02-05
nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h
Timothy Pearson
2016-02-05
nb/amd/mct_ddr3: Work around RDIMM training failure
Timothy Pearson
2016-02-04
northbridge/intel/peg: Disable unused ports
Patrick Rudolph
2016-02-04
nb/intel/sandybridge/raminit: Fix two dimms per channel
Patrick Rudolph
2016-02-02
src: Fix various spelling and whitespace issues.
Martin Roth
[prev]
[next]