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2015-04-09northbridge/amd/agesa/familyXY: Make NULL device op explicitEdward O'Callaghan
Use 'DEVICE_NOOP' macro introduced in: commit 530355d include/device/device.h: Provide DEVICE_NOOP macro shim to provide formalism. Make the null device ops here explicit and in-line with formalism elsewhere. Change-Id: I2400b29a5108a6bae21959177e53321810ca1407 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8035 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
With kconfig understanding wildcards, we don't need Kconfig files that just include other Kconfig files anymore. Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9298 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-06global: Refactor get_option usageVarad Gautam
Restructure get_option() calls to avoid unnecessary return value checks by pre-assigning defaults to the options being retrieved. Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4 Signed-off-by: Varad Gautam <varadgautam@gmail.com> Reviewed-on: http://review.coreboot.org/8631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-05intel/nehalem: rename copypasted smi finalizer functionAlexander Couzens
The nehalem smi finalize handler was just copied from sandybridge, without even changing the function name. TEST=Built and tested on x201t with additional patch to use finalizers Change-Id: Ifb44eeaaa6e03556deeb5d12ed1147e02d6d6eb9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8292 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-04-04build system x86: deprecate bootblock_lds and ldscripts variablesPatrick Georgi
Instead of keeping this separate variable around, add linker scripts to the $(class)-y source lists and let the build system sort things out. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I4af687becf2971e009cb077debc902d2f0722cfb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-02northbridge/amd/amdfam10: Generate SMBIOS tables for RAMTimothy Pearson
TEST: Booted ASUS KFSN4-DRE and verified SMBIOS contents via dmidecode utility. Change-Id: Id656f2f6cf5a4ecafa03e150ad91f69107a4fe88 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-04-01mainboards/amdfam10: Copy DIMM information to cbmem after romstageTimothy Pearson
src/northbridge/amd/amdfam10: Add amdmct_cbmem_store_info() function. Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the Makefile's were updated to use named types for cbfs file addition. However, the call sites were not checked to ensure the types matched. Correct all call sites to use the named types. Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9195 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-01northbridge/amd/amdfam10: Collect DIMM information for ramstage useTimothy Pearson
1.) Allow MCT information structures to be copied to cbmem. 2.) Retrieve DIMM vendor, model, and serial information. 3.) Allow maximum installable memory to be set via devicetree. Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9137 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-01northbridge/amd/amdmct: Pack MCT and DCT info structsTimothy Pearson
This allows safe access of romstage MCT values from ramstage Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9158 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-28build system: normalize linker script file namesPatrick Georgi
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9107 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-27northbridge/amd/amdfam10: Properly implement SLIT generationTimothy Pearson
Change-Id: I973abf2224762bf7a53d71177544ade15db50cba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8856 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-19cpu/amd/model_10xxx: Add support for early cbmemTimothy Pearson
mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. The CBMEM location code implicitly assumes TOM does not change between romstage and ramstage. TOM is set by romstage raminit, and is never changed by romstage or ramstage afterward. As the CBMEM location is positioned at a specific offset from TOM that is known to both romstage and ramstage early CBMEM is safe on Fam10h systems. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8489 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-19northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMATimothy Pearson
The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA is enabled, however when GFXUMA is disabled an attempt was made to locate the CBMEM memory segment above the I/O hole in certain rare cases. Removing this special case does not impact functionality, and paves the way for early CBMEM support. Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8664 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Aaron Durbin <adurbin@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17cpu/amd/model_10xxx: Move GFXUMA size calculation to separate functionTimothy Pearson
This is required for early CBMEM support. Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8663 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-16northbridge/amd/pi: Create common agesawrapper.cDave Frodin
This removes the mainboard agesawrapper.c file from binarypi based boards and creates a common one. Change-Id: I900dba914f1c401e4ac732eb93d94b98216e629a Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8671 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16cpu/amd/pi: Add amd_initcpuio() and amd_initmmio()Dave Frodin
This makes the change to the cpu/amd/pi/00730F01 that was made for the cpu/amd/agesa based boards in: commit 48518f0d AGESA: Add amd_initcpuio() and amd_initmmio() These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). The equivalent change has already been made for cpu/amd/pi/00630F01. Change-Id: I591b50ee807436f5a1dee14d2c88a77462024744 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8670 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16northbridge/i945/gma: fix build error with native graphics initFrancis Rowe
Tested on an X60, Native graphics init still works perfectly. Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/8696 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-03-15northbridge/amd/amdht/h3finit.c: Fix boot failureTimothy Pearson
GIT hash 586d6e introduced a regression that causes boot failure with an f0011449 AMD stop code. Change-Id: Ieced9088b79bc89d55117b7240b82a086eff9d21 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8685 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-13northbridge/amd/amdht: Allow mainboards to set HT frequency limitTimothy Pearson
This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8464 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-13northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSPAlexander Couzens
This capability means: FERR messages are sent out on system detected an unmasked floating point x87 FPU error. Even though this capability is supported on nehalem it doesn't make sense to set it in early stage. This MSR has a core scope which results in an unsync MSR because it's not set on other cores than the BSP. Found-by: BITS Tested-on: lenovo thinkpad x201t Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8659 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-10ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki
There is nothing platform specific in retrieving S3 resume state from romstage_handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8188 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10northbridge/amd/pi: Remove superfluous logic operandDave Frodin
Commit 2e0cf14 corrected this for pi/00730F01/northbridge.c. This commit fixes it for pi/00630F01/northbridge.c. Found-by: Clang Change-Id: I4eb93a07aacf6ffc5a159222117e7c934d85859e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8289 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-10AMD Bald Eagle: Add northbridge files for new AMD processorBruce Griffith
Also fix a typo in a config option for SteppeEagle. Change-Id: Iad51cc917217aa0eac751dc805c304652d20e066 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7247 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-09AMD fam10: Drop PCI_BUS_SEGN_BITSKyösti Mälkki
All boards in tree use 0. Looks like this is all work that was never completed and tested. We also have static setting sysconf.segbit=0 which would conflict with PCI_BUS_SEGN_BITS>0. Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support to cover over 255 buses. Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09AMD fam10: Fix include of conf.cKyösti Mälkki
Change-Id: I982acb0b36f2cef8281ffbac4511f831f08fc89a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8553 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09AMD fam10: Remove __PRE_RAM__ from ramstage-only codeKyösti Mälkki
Change-Id: I41aba81def13c99671eb609dd1e76a9a45299622 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8552 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD fam10: Always have AMDMCTKyösti Mälkki
Also drop some more #if UNUSED_CODE. Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD K8: Fix allocation size for HyperTransport linksKyösti Mälkki
There is no requirement that in dev->link_list the last element would have the highest link->link_num. Also fix off-by-one error when allocating for more links. Change-Id: Id8a7db3ffb4111eb31e70ea14fd522b70368dd8c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8550 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD K8: Move the test for connected HyperTransport linkKyösti Mälkki
Change-Id: I7f8cbfcae7ec2a49e91ceda1eecdcf76b2137d8b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8549 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-07northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and laterTimothy Pearson
The BKDG for K10 revision D and later processors recommends a smaller MCT burst write queue depth when using unganged memory. TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431 processors. Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8500 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-07AGESA: Move agesawrappers related to HAVE_ACPI_RESUME supportKyösti Mälkki
This change brings all agesawrappers in a single file to make it easier to understand the actual execution flow. Change-Id: Ifbb2b16e4cccfaa17aaf10887a856797be9b6877 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8605 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07AGESA: Use same HeapManager for all BiosCallOutsKyösti Mälkki
We do not allow platforms to mess around with memory layout. Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04cpu/amd/model_10xxx: Refactor model detection to reduce code duplicationTimothy Pearson
Moved mctGetLogicalCPUID() to a separate file and made it available in both romstage and ramstage. Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8499 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-03northbridge/amd/amdmct: Add revision D to K10 revision mask listTimothy Pearson
Change-Id: Ib5f87bdc50c0bca370a636218d3b5d4cc9157c12 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8501 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-01devicetree: Drop redundant scan_bus() opsKyösti Mälkki
Change-Id: If96e0843f507b9f1db9977b5d0c47f5ed1c59999 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8533 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01AGESA fam16: Drop HyperTransport scanKyösti Mälkki
Already done for fam15tn/rl. Change-Id: Id74ca13610a4ef407c866a4419139287413078a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8531 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-20AMD binaryPI: Drop HT3_SUPPORTKyösti Mälkki
Kconfig variable is not implemented. Also fix broken abuild. Change-Id: I569f44e97abc570158472ddbd0f890315233f8a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8494 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-20AMD fam10: Refactor variables in scan_chainKyösti Mälkki
We only need one of devx and dev. This function should be called with dev already adjusted if link_num > 3. Change-Id: I7166bbb88143bc28802c9530c4da16db67868d8e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8351 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20AMD fam10: Move the test for connected HyperTransport linkKyösti Mälkki
Change-Id: I9a24f9897115ce37ee11ca41c8b74142c95fc534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8350 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20AMD K8 fam10: Refactor offset_unitid configurationKyösti Mälkki
Change-Id: I198f2ad321e1a8b6d932f5624b129e312e36a309 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8349 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20AMD amdfam10: Always have HT3_SUPPORTKyösti Mälkki
Change-Id: I6ce784fd9e7a6876a37c910c503fafa3a17bf96f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8348 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20AMD K8 fam10: Drop link_num from scan_chain parametersKyösti Mälkki
Change-Id: Id8fc1d7d8a23238e6848cd2cf4270d782e90a7d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8347 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20AMD K8 fam10: Remove some excessive preprocessor useKyösti Mälkki
Change-Id: Iee51c51b662d1f5e3d918d1e5b961f06c6b99df6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8346 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-19sandybridge: Try lower frequency if PLL didn't lock.Vladimir Serbinenko
Change-Id: I2c2d586fc572b78b5019f8ef2714959799a8d2a9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/8480 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-18amd/00730F01: Move SteppeEagle specific settings to northbridgeDave Frodin
These settings are specific to the SteppeEagle SOC and should be made in its northbridge code rather than the CPU code. Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8254 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-17sandybridge/raminit: Get max mem clock from devicetreeAlexandru Gagniuc
Note that the limit is not set in the devicetree.cb which use native sandybridge raminit, as it is not needed. When that isn't set, it's automatically set to zero, and when we find that, we automatically return the default limit. Thus behavior isn't changed for any board. Change-Id: I447399eea71355612b654710a56f3a0077c2f7f9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8476 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-17sandybridge/raminit: Do not die() if timC calibration failsAlexandru Gagniuc
We can successfully bring up systems if timC calibration fails, as has been demonstrated with google/butterfly. As a result, do not die(), but simply print a message and continue in the hope that we may be able to boot. Change-Id: I49ec80324f63b2d45ae8f61c5c26454acb9c232f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8475 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 13:25:53 +0000