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path: root/src/northbridge
AgeCommit message (Expand)Author
2012-11-30Rename devices -> deviceStefan Reinauer
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
2012-11-27Drop driver-y from GM45/ICH9/RK9Stefan Reinauer
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
2012-11-27Get rid of drivers classPatrick Georgi
2012-11-27intel/gm45: new northbridgePatrick Georgi
2012-11-24yabel: Use X86_* instead of the more verbose M.x86.REG_*Patrick Georgi
2012-11-24x86 realmode: Use x86emu register file + definesPatrick Georgi
2012-11-24x86 realmode: Adapt to x86emu/YABEL style return codesPatrick Georgi
2012-11-24x86emu: Move realmode handler into own directoryPatrick Georgi
2012-11-17Drop no-op bootblock.cKyösti Mälkki
2012-11-17Use new system agent binariesStefan Reinauer
2012-11-14VIA chipsets: fix compilation without real mode codeStefan Reinauer
2012-11-14Sandybridge: Set PEG clock gatingMarc Jones
2012-11-14Add PCIe init and NMode flag to PEI data structureStefan Reinauer
2012-11-14Add ddr3lv_support flag to pei_data structureDuncan Laurie
2012-11-14pei_data.h: Fix commentMarc Jones
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
2012-11-12Initial IGD OpRegion implementationStefan Reinauer
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
2012-11-09Make coreboot use the offset parameter in cbfstool createStefan Reinauer
2012-11-09Make register/value lists constStefan Reinauer
2012-11-07SandyBridge/IvyBridge: Use flash map to find MRC cacheStefan Reinauer
2012-11-07Add missing newline in error messageStefan Reinauer
2012-11-07AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPUSiyuan Wang
2012-11-07CMOS: Move MRC seed offset into upper bankDuncan Laurie
2012-11-07AMD rd890 late.c: Don't enable PCIe ports after PCIe init.Siyuan Wang
2012-11-07AMD agesa family15: PCI domain should scan bus from 0x18.0Siyuan Wang
2012-11-02Fix some issues with new "reference" toolchainStefan Reinauer
2012-10-26northbridge/sch: move the \n so it reads a little betterSebastian Andrzej Siewior
2012-10-26northbridge/sch: read the size of main memory from the proper registerSebastian Andrzej Siewior
2012-10-26northbridge/sch: Read the GPU memory from the correct PCI deviceSebastian Andrzej Siewior
2012-10-26northbridge/sch: don't overwrite hightables with GPU / TSEG memorySebastian Andrzej Siewior
2012-10-08hpet: common ACPI generationPatrick Georgi
2012-10-07Remove chip.h files without config structureKyösti Mälkki
2012-09-25HAVE_HIGH_TABLES is gonePatrick Georgi
2012-09-19agesa fam15 northbridge: change lapic_id to accommodate two CPUsSiyuan Wang
2012-08-28Fix AMD UMA for RS780Kyösti Mälkki
2012-08-27AMD northbridges: factor out CPU allocationKyösti Mälkki
2012-08-27AMD northbridges: rewrite CPU allocationKyösti Mälkki
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
2012-08-09Sandybridge: Fix integer overrun in romstage udelay()Stefan Reinauer
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
2012-08-07Sandy/Ivy Bridge and Cougar/Panther Point: Fix namesStefan Reinauer
2012-08-05AMD f15: Change multiply ONE_MB to bit shifting (Propagation)zbao
2012-08-04AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation)zbao
2012-08-04AMD NB: Limit the device field to 5 bits. (Propagation)zbao
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