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2018-08-09src/northbridge: Fix typoElyes HAOUAS
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Correct number of MCA banks clearedMarshall Dawson
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
This patch contains the parts that changed the hash of the generated binary; probably due to the compiler optimizing things slightly different. Change-Id: I3233ba1747dcf5ad05b2ad771a86e3936f655d1c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-04nehalem/raminit: remove read_mchbar functionsFelix Held
Change-Id: I7935cc166aa39f4053f45eef925d92ce50fd98ba Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-04nehalem/raminit: clean up code and remove write_mchbar functionsFelix Held
This part of the cleanup patches changes the hash of the output binary; likely due to the compiler optimizing things differently. Change-Id: I1a22f6216a75e2b463d4e169e97ad6e0bbaafae8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27708 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-04northbridge/nehalem: add MCHBAR8/16 AND_OR macrosFelix Held
Change-Id: I62e4a8610689e72944e1a9c020f13a47d402c136 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-04nehalem/raminit: clean up code and use MCHBAR macrosFelix Held
On a a timeless build with coreboot i386 crossgcc 6.3.0, this doesn't change the hash of the output binary. Change-Id: I15e09320e72cffb8a2617eca0cfe40780f74bece Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27707 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-04nehalem/raminit: remove REAL define and most dead codeFelix Held
The code only compiled when REAL was set to 1; the other case included an unpublished include. Change-Id: I7f31e9cd02f45492d6c9e88ec6164a537ca5e3c2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27706 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03sandybridge/raminit_mrc: remove reference to report_platform_info()Matt DeVillier
Commit ef8c559e537ed10d8054ca6a72ca50e0531fde95 [nb/intel/sandybridge/report_platform: Move remaining code to sb folder] moved reporting code to the southbridge, but missed a reference in the non-default MRC raminit path (so testing missed it). Remove invalid reference to fix compilation error. Test: build google/link with MRC raminit option selected Change-Id: I270a95ac53fbc9f8792f375908cf91585261f6a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining placesFelix Held
Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sandybridge/raminit_common: use macro for execute command queue registerFelix Held
This patch doesn't change the hash of a timeless build. Change-Id: I5d329f65be0eee741fd330c0926881ff4f956624 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sandybridge/raminit_common: use FOR_ALL_CHANNELS macroFelix Held
Change-Id: I01bd69605760e8a03787dcfa3da9f47576e3144a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
This patch contains the parts that changed the hash of the generated binary; probably due to the compiler optimizing things slightly different. Change-Id: Ide0b3296864e24edb646956e47221bfef8182e3d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27725 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the resulting binary doesn't change with applying this commit. Change-Id: I2b1dc8befa3381f3edac06704e31e7ef50f86fa4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27724 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held
Change-Id: I5d91674ebd281a595e7c0462671f4715ca09cb5c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27723 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/gm45: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27242 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/pineview: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27243 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27245 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/sandybridge: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27244 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the resulting binary doesn't change with applying this commit. Change-Id: I057abe314622e92000c7e4ff2faa4595edb5244b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
Change-Id: Ie95321f3eb6fb17b17eb25e8a54670654c373706 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30northbridge/nehalem: add MCHBAR AND/OR/AND_OR macrosFelix Held
The newly added macros are used for cleaning up the RAM initializatiion code. Change-Id: I3d3782ee1fa524cf69b63ccc7eb73e9a2ace84ec Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30northbridge/nehalem: clean up header fileFelix Held
* remove duplicate macro definitions * add brackets to macros Change-Id: I1f758203afdcb1b18f3c0d786698f9fbf2246e0e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-29sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held
Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held
Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph
Commit 74203de "intel/sandybridge: Don't hardcode platform type" changed the MRC layout. Bump the version to prevent a boot error, if the cache isn't cleared on flashing a new coreboot version. Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27712 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
* Add a function to return CPU platform ID bits * Add a function to return platform type ** Platform id is 4 on Lenovo T430 (mobile) ** Platform id is 1 on HP8200 (desktop) * Use introduced method to handle platform specific code * Use enum for platform type * Report platform ID Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-26nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus widthPatrick Rudolph
The bus width has to be encoded where the lower 3 bits are the bus width in multiple of 8 and the following two bits give the error checking bits in multiple of 8. Hardcode to 64 bit as done on haswell. TODO: Make it dynamic once there's ECC support. Change-Id: I3b83a098205455b1c820d0436c6984938f261466 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-26nb/intel/sandybridge/raminit: Fix PDWN_mode on desktopsPatrick Rudolph
On desktop boards the PPD bit of MRS register MR0 is set and thus DLL_Off mode shouldn't be used, as enforced by datasheet 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.17.1. Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-26nb/intel/nehalem: Remove the C native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I9228fa7eadfe2a827c1f4de9d6710b60d3f1b121 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25nb/intel/sandybridge/raminit: Fix non ASCII charPatrick Rudolph
Change-Id: I3f0869dc0b72bef7da8313c69da4fe2a63761ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27633 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25nb/intel/sandybridge/raminit: Set REFIx9 according to specPatrick Rudolph
Set tREFIx9 to 8.9*tREFI/1024 as suggested in xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1. Use the minimum value of REFI*8.9 and tRASmax as suggested by 3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9. Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-23AGESA binaryPI: Remove code for CONFIG_CBB!=0Kyösti Mälkki
These are single-node platforms with CONFIG_CBB==0 everywhere in the tree. Remove guarded code that was not built. Change-Id: I6118249937e6c8032acd78018c7c83b1da078f7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-20AGESA binaryPI: Fix and optimize for MAX_NODES_NUMKyösti Mälkki
With nodeid<8, CONFIG_CDB==0x18, PCI device number does not overflow. CONFIG_CDB is not a value we can configure. Change-Id: I23e9707a8ec12dcd80c00688d6237d085d1abf36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-07-12nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMsElyes HAOUAS
Change-Id: Ib1f999447b37a1524d589552ea2eec640c2a2c7e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/18387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-02src/nb: Fix non-local header treated as localElyes HAOUAS
Change-Id: I8174d7b40008cfe4fba10fde4670682aac0ad078 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from/supersedes https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27269 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-29sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans
For this to work the northbridge and lpc bridge device need acpi_name functions. TESTED on Thinkpad X200, a valid PIRQ routing in SSDT in /sys/firmware/acpi/tables/SSDT Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-23nb/intel/i945: Remove dead codeElyes HAOUAS
Regarding "Intel 945G/945GZ/945GC/945P/945PL Express Chipset Family", Document Number: 307502-005, page 91, if Channel B is empty, all of the C1DRBs are programmed with the same value as C0DRB3. Mobile 945 express chipset datasheet doesn't mention this specific case. Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27204 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-20nb/intel/e7505: Leave ROM as un-cacheable in postcarKyösti Mälkki
Collected timestamps indicate LZMA decompression of ramstage is 4x slower when ROM is marked WP-cacheable, in contrast to having ROM as US. A simple copy WP->WB with uncompressed ramstage also appeared to be twice as slow as UC->WB copy. It should be noted that if POSTCAR_STAGE was removed from build, un-lzma takes 130 seconds instead of 45 milliseconds. Change-Id: I2cf995395ef2d303ad0bc044dbfa160990a705d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
Boot tested on asus/p2b-ls and p2b-ds. Change-Id: I0154f1d120bef3b45286fb4314f0de419cd8341e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/26821 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-17nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I96f42d5dc10d36855bdca64d1406a254250ee5b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26820 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-07 02:15:03 +0000