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2021-02-04nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`Angel Pons
This partially reverts: - Commit 77d3b655ed - Commit 487c1a24f5 - Commit 875c21f491 - Commit c4d1b47ad9 - Commit b96c358751 - Commit 9cbf26d18e It is intentional to use <device/pci_ops.h> whenever one needs to use PCI config access. The bootblock.c files needing I/O config do not need to be an exception to this. Change-Id: Ifba05717dad404a844618815c5347a05e07a3362 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-04src: Remove useless comments in "includes" linesElyes HAOUAS
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02treewide [Kconfig]: Remove useless commentElyes HAOUAS
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also replace 'reg' with 'reg32'. Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49537 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Change-Id: Ib370fc1bae017d084844eece44799676a657323b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also rename 'reg' to 'reg32'. Change-Id: Id741f636162a8a228bca069637993422deb5e09c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also rename 'reg' to 'reg32'. Change-Id: Ie8dd238a8f10daad9653f44b3ada329c3ede58fe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also rename 'reg' to 'reg32'. Change-Id: I3aca03dfe20dd0a61cba3ba55146f76e412a2c5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BARAngel Pons
They aren't necessary. Removing them changes the binary because the corresponding access macros no longer perform pointer arithmetics. Change-Id: I9723a00b58ee35befdce6a3a51aa2b1fce8efa80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49745 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01nb/intel/haswell: Calculate TSEG limit from registersAngel Pons
Done for consistency with other northbridges. Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-01nb/intel/haswell: Create RMRR for iGPUAngel Pons
Taken from Broadwell. Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-30nb/intel/i945: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/gm45: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I635f3615f566502f79bbd81f9f743ce63bba3b1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49758 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/x4x: Define and use MMCONF_BUS_NUMBERAngel Pons
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Moreover, the ASL reservation for MMCONFIG was only for 64 busses. Change-Id: I7366a5096aacd92401535be020358447650b4247 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/pineview: Define and use MMCONF_BUS_NUMBERAngel Pons
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhereAngel Pons
Bootblock enabling needs some special handling. Also, the definition of the `get_pcie_bar` function is incorrect for Ironlake, so remove it. With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work. However, it has not been tested. Using 256 busses should still work. Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: Id88c18129bb773d979ad84bd0bb47188d74d4bc4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49762 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/haswell: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I0d6338f763a78895b1ae14d1ab68253851b6c283 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49763 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/ironlake: Use RCBA macrosAngel Pons
Use defined RCBAx macros over readX/writeX calls. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I87cae75268ef5f329001706e4771e98653d40cd1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50037 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27nb/intel/haswell/haswell.h: Do not include `pch.h`Angel Pons
Avoid indirect header inclusion, include `pch.h` where necessary. Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-27sb,soc/amd: Rename PMOD to PICM in ASLKyösti Mälkki
Use the same variable name as soc/intel to implement a common _PIC method at top-level ASL. Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25nb/intel/ironlake: Drop constant parameterAngel Pons
All callsites of `rmw_1d0` use the same `flag` value. Change-Id: I84fab5d3fd270ce684cd6ca892c213b0d8610283 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-25nb/intel/sandybridge: Only run DMI recipe on Ivy BridgeAngel Pons
Reference code does not run any DMI recipe for Sandy Bridge. Create a helper function and exit early for Sandy Bridge. The CPUID value will be used in a follow-up, since DMI setup has stepping-specific steps. Change-Id: I5d7afb1ef516f447b4988dd5c2f0295771d5888e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48413 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25nb/intel/sandybridge: Correct late DMI init sequenceAngel Pons
Based on reference code, update the DMI ASPM setup steps. Change-Id: I1248305b2f76f48f4e6910de1a6980e942f16945 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48536 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24cpu/intel/haswell: Set C9/C10 vccminAngel Pons
Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell. Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZEElyes HAOUAS
Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE". It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets should have at least 256K L2 cache. That is plenty for XIP RO cache of bootblock + romstage and a 32K CAR. Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-01-19nb/intel/pineview/northbridge.c: Fix overlapping resourcesArthur Heymans
Fixed resources should not overlap. Change-Id: I166e0095ac0cc0dd8271a693bb452f505a1a9413 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19nb/intel/pineview/northbridge.c: Improve readabilityArthur Heymans
This cosmetic change does 2 things: - change bitwise shifting to division - Make the division by / KiB explicit for fixed legacy ranges like 0xa0000. Change-Id: Ia6c2ee29e37040ea9b11505e9888c7f6f8da78bc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19nb/intel/i945/northbridge.c: Reserve upper part of lower memoryArthur Heymans
This memory is used for option roms and BIOS. This matches the ACPI code. Change-Id: I53dd4b967569889108352ca70086a12ce252e8e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19nb/intel/i945/northbridge.c: Improve readabilityArthur Heymans
This cosmetic change does 2 things: - change bitwise shifting to division - Make the division by / KiB explicit for fixed legacy ranges like 0xa0000-0xbffff. Change-Id: I626989fa6625e0b3613a11e709c614d40a788b0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19nb/intel/ironlake/northbridge.c: Fix overlapping resourcesArthur Heymans
Fixed resources should not overlap. Change-Id: I7a70f5475c1d701db2cb8cbea659bacf6d0c52ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19nb/intel/ironlake/northbridge.c: Improve readabilityArthur Heymans
This cosmetic change does 2 things: - change bitwise shifting to division - Make the division by / KiB explicit for fixed legacy ranges like 0xa0000-0xbffff. Change-Id: If4e05f496abc05e06a944b244824376f3937a57b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19nb/intel/ironlake/ironlake.asl: Remove sandy bridge copy pastaArthur Heymans
Change-Id: Ic5a49a81a886aecde0fbaae3ecfa6b0504a4e3ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19nb/intel/ironlake: Remove chromeos copy pastaArthur Heymans
Change-Id: Ic2582dbf70e11e0566ba525c72300a6248807512 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19nb/intel/ironlake: Print MCH dev/revision IDs and CAPIDAngel Pons
Given the lack of documentation for this platform, having this info in coreboot logs (e.g. from board_status) can be pretty useful. Change-Id: I6a743c1efc1b6da71589460a69bfe4785e3e77a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-18nb/intel/gm45: Reserve MMIO and firmware memory below 1MiBNico Huber
It looks like we didn't care to reserve the VGA MMIO (a & b segments) and the c..f segments, initially. It was probably never needed until the new resource allocator that will make use of any unclaimed space. Change-Id: Iebdae64914d9f8301cafc67a5aba933c11294707 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18Revert "nb/intel/gm45/gm45.h: Remove duplicated include"Patrick Georgi
This reverts commit 27af8a7e5df435d93547061a3273ec4de45f0080. Reason for revert: This depends on CB:45517 which hasn't landed yet. Change-Id: I2a6fbf54cfe01bf25e9ea8da84f6f2a17418f0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/49647 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18northbridge/intel/x4x/dq_dqs.c: Remove repeated wordElyes HAOUAS
Change-Id: Iee24c6bf82ab6ff6691707ed0c388cfe492cc925 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18northbridge/intel/gm45/bootblock.c: Remove repeated wordElyes HAOUAS
Change-Id: Ie3bfdb27aa7c981a500e82b6a6958576e0048bcd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18northbridge/intel/x4x/raminit_ddr23.c: Remove repeated wordElyes HAOUAS
Change-Id: I9763499ad5cf0395c83770908a277f089ceed475 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18northbridge/intel/sandybridge/bootblock.c: Remove repeated wordElyes HAOUAS
Change-Id: I9e723e1d31b093a4781413efe7f290a295b833dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18nb/intel/gm45/gm45.h: Remove duplicated includeElyes HAOUAS
Change-Id: Iabd6c69cd4c28f0015d4cf1f95d5ae0b6dc8b47e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18lib/ramtest: Fix ram_check() declarationsKyösti Mälkki
For a long time, second parameter 'stop' has been ignored. The tested range is within 1 MiB above 'start'. Change-Id: Icbf94cd6a651fbf0cd9aab97eb11f9b03f0c3c31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48561 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15nb/intel/sandybridge: Clarify command timing calculationAngel Pons
Command timing is the absolute value of the most negative `pi_coding` value across all ranks, or zero if there are no negative values. Use the MAX() macro to ease proving that `cmd_delay` can never be negative, and then drop the always-false underflow check. The variable type for `cmd_delay` still needs to be signed because of the comparisons with `pi_coding`, which is a signed value. Using an unsigned type would result in undefined and also undesired behavior. Change-Id: I714d3cf57d0f62376a1107af63bcd761f952bc3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-15nb/intel/sandybridge: Fix handling of clock timingAngel Pons
Clock is a differential signal and propagates faster than command and control, therefore its timing needs to be offset with `pi_code_offset`. It is also a periodic signal, so it can safely wrap around. To avoid potential undefined behavior, make `clk_delay` signed. It makes no difference with valid values, because the initial value can be proven to never be negative and `pi_code_offset` is always positive. With this change, it is possible to add an underflow check, for additional sanity. Change-Id: I375adf84142079f341b060fba5e79ce4dcb002be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-15nb/intel/sandybridge: Remove wrong and nonsense conditionAngel Pons
Commit 7584e550cc (nb/intel/sandybridge: Clean up program_timings) introduced this condition along with a comment that says the opposite. Command and clock timings always need to be computed, so drop both the nonsensical condition and the equally-worthless corresponding comment. Change-Id: I509f0f6304bfb3e033c0c3ecd1dd5c9645e004b2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-15nb/intel/x4x: Clean up raminit commentsAngel Pons
Use C-style comments everywhere, and follow the coding style. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I3ef96c5f6553ad50cee7d7f5614128b62a89e4ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-15nb/intel/x4x: Reset DQS probe on all channelsAngel Pons
Eaglelake MRC 2.55 does this, and also stalls for less time. Change-Id: Iaaefd32c341a490e5c129df865407ec3f8da8212 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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