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path: root/src/northbridge
AgeCommit message (Expand)Author
2020-09-14nb/intel/ironlake: Reserve gap betwen TSEG and BGSMNico Huber
2020-09-14nb/intel/ironlake: Use an `index` variable for resourcesNico Huber
2020-09-08nb/intel/ironlake: Use an enum for `gpu_panel_port_select`Angel Pons
2020-09-08nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`Angel Pons
2020-09-08nb/intel/haswell: Drop `gpu_panel_port_select`Angel Pons
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
2020-08-31nb/intel/sandybridge: Add ECC error injection register informationAngel Pons
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
2020-08-24nb/amd/agesa: define DDR3_SPD_SIZE as a common valueMike Banon
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
2020-08-17nb/amd/agesa: read 256 bytes to SPD buffer instead of 128Mike Banon
2020-08-17src: Use PCI_BASE_ADDRESS_* macros instead of magic numbersElyes HAOUAS
2020-08-17nb/intel/x4x/raminit_ddr23.c: Remove dead assignmentElyes HAOUAS
2020-08-12nb/intel/sandybridge: Add comments to `struct iosav_ssq`Angel Pons
2020-08-11nb/intel/sandybridge/raminit: Add commentsPatrick Rudolph
2020-08-11nb/intel/sandybridge/raminit: Fix ECC scrubPatrick Rudolph
2020-08-11nb/intel/sandybridge/raminit: Add ECC debug codePatrick Rudolph
2020-08-06nb/intel/sandybridge: Drop inexistent device from DMARAngel Pons
2020-08-06nb/intel/sandybridge: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-06nb/intel/sandybridge: Refactor `get_pcie_bar`Angel Pons
2020-08-05{nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik
2020-08-05src: Use space after 'if', 'for'Elyes HAOUAS
2020-08-05src: Use space after switch, whileElyes HAOUAS
2020-08-04nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons
2020-08-04nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDsAngel Pons
2020-08-04nb/intel/x4x: Remove dead assignmentsAngel Pons
2020-08-04nb/intel/x4x: Refactor `decode_pcie_bar`Angel Pons
2020-08-04nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/i945: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/i945: Refactor `get_pcie_bar`Angel Pons
2020-08-04nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons
2020-08-04nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntaxAngel Pons
2020-08-04nb/intel/sandybridge: Update to ASL 2.0 syntaxAngel Pons
2020-08-04nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons
2020-08-04nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/pineview: Refactor `decode_pcie_bar`Angel Pons
2020-08-04nb/intel/pineview: Change signature of `decode_pciebar`Angel Pons
2020-08-04nb/intel/pineview: Use `MiB` definitionAngel Pons
2020-08-04nb/intel/pineview: Remove dead assignmentsAngel Pons
2020-08-04nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons
2020-08-04nb/intel/gm45: Use PCI bitwise opsAngel Pons
2020-08-04nb/intel/i440bx: Make ROM area unavailable for MMIOKeith Hui
2020-08-03nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Physical Layer registersAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Physical Layer device definitionAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Link register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Add definition for QPI Link PCI deviceAngel Pons
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