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2018-01-31nb/intel/*.h: Remove left-over register definitionsPatrick Rudolph
The code has been moved into drivers folder. Change-Id: I122affffd5108052ed7a95b34d0d66a6d3279d41 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-26nb/intel/sandybridge: Use common mrc cache functionsArthur Heymans
This uses the functions in include/mrc_cache.h instead of northbidge/intel/common/mrc_cache.h Tested working on Lenovo Thinkpad x220, mrc_cache region gets written and S3 resume still works fine. Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24AGESA f15 cimx/sb700: Remove unused chips codeKyösti Mälkki
Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23binaryPI: Move agesawrapper.h headerKyösti Mälkki
Change-Id: Ib8d4d3ee490188ce171188d859549da586683e26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23AGESA_LEGACY: Apply final cleanup and file removalsKyösti Mälkki
With no boards left using AGESA_LEGACY, wipe out remains of that everywhere in the tree. Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-23nb/intel/i945: Use ESMRAMC instead of 0x9eElyes HAOUAS
Macro renamed to be in accordance with the name used in the datasheet. Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-18Intel i82810 boards & chips: Remove - using LATE_CBMEM_INITKyösti Mälkki
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i82810 Mainboards: src/mainboard/asus/mew-am src/mainboard/asus/mew-vm src/mainboard/ecs/p6iwp-fe src/mainboard/hp/e_vectra_p2706t src/mainboard/intel/d810e2cb src/mainboard/mitac/6513wu src/mainboard/msi/ms6178 src/mainboard/nec/powermate2000 Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23300 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17vx900: decode the whole ROMLubomir Rintel
Fixes supports for flash ROMs larger than 512K, such as the 1M one in HP t5550 Thin Client. Change-Id: I4d6287e130809c33dfbd40bce7913a95b4b3a9c7 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15Intel i82830 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i5000 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i5000 Mainboards: mainboard/supermicro/x7db8 mainboard/asus/dsbf Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i855 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i855 Mainboards: mainboard/lanner/em8510 Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15AMD GX2 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/amd/geode_gx2 northbridge/amd/gx2 southbridge/amd/cs5535 Mainboards: mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15vx900: skip remap of high memory ranges if unnecessaryLubomir Rintel
If the DRAM does *not* actually overlap the PCI space, the remap code notices it is the case, but for some reason proceeds with the remapping, attempting to remap a negatively sized chunk. Bummer. With a single 1024M (two ranks of 512M) module: Nothing to remap Mem remapping enabled Remapstart 5120(MB) Remapend 6144(MB) Top of RAM 1024MB New top of RAM 2560MB Wrote remap map a0101 Mem remapping enabled Remapstart 4096(MB) Remapend 2560(MB) New top of memory is at 2560MB Needless to say, subsequent ram_resource() ruins the memory map for the OS -- Linux won't boot without a mem= argument and memtest quickly. TEST=memtest and Linux boot on HP t5550 with 1024M of memory Change-Id: Ic221723a26c5d1a03bf34c7722b0abe115f456ba Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15vx900: map the SPI controllerLubomir Rintel
This is required for Flashrom to work well. Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15vx900: fix format strings for DEBUG_RAM_SETUP=yLubomir Rintel
Change-Id: I990969cf1389c19032c4a0fafbdef45b9d6d1e8b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-05nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeoutArthur Heymans
Especially on ICH7 failing to do so results in i2c block read being unusable. On ICH10 this problem doesn't manifest itself that much. This moves disabling the watchdog reboot to the northbridge code like i945 (even though it technically is southbridge stuff). TESTED on Intel DG41WV: hacking on raminit is much nicer since no need to do a hard power down for +4s are needed to clear the timeouts. Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-12-20intel/gma: fix RPNFREQ_VAL bitmaskFelix Held
gma.c of Nehalem was copied from Sandy/Ivy Bridge, so fix it there too. Tested on lenovo/x230. Since both the bit that was masked wrongly and the one that wasn't masked, but sould have been, are 0, the behaviour on lenovo/x230 doesn't change. Change-Id: I5f51c4929df83f948fcb7dc06e07ac3cc4ccf4f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/22596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-12-19nb/intel/nehalem/gma: Drop stale pre-pocessor guardsNico Huber
These were forgotten when updating the caller and resulted in build failures for every but the NGI path. Change-Id: I2490a3b4dca6c248eb37f43aa676ae619afdbfc7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-16nb/x4x/raminit: Rewrite SPD decode and timing selectionArthur Heymans
This is mostly written from scratch and uses common spd ddr2 decode functions. This improves the following: * This fixes incorrect CAS/Freq detection on DDR2; * Fixes tRFC computation; tRFC == 78 is a valid timing which is excluded and 0 ends up being used; (TESTED) * Timings selection does not use loops; * Removes ddr3 spd decode and is re-added in follow-up patches using common ddr3 spd functions; * Raminit would bail out if a dimm was unsupported, now in some cases it just marks the dimm slot as empty; * It dramatically reduces stack usage since it does not allocate 4 times 256 bytes to store full SPDs, amongs other unused things that were stored in sysinfo; * Reports when no dimms are present; * Uses i2c block read to read SPD which is about 5 times faster than bytewise read, with a fallback to smbus mode in case of failure, which does seem to happen when the system is forcefully powered off. Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-12nb/intel/x4x/rcven.c: Fix programming coarse offsetArthur Heymans
This fixes some bitwise logic errors that caused the coarse offset not to be programmed. This fixes a regression introduced by 6d7a8c "nb/intel/x4x/raminit: Rework receive enable calibration" where the coarse offset doesn't get programmed anymore. TESTED on Foxconn g41s-k on a DIMM where the final DQS receive enable delays are close but above and below the edge of a coarse delay setting. Change-Id: I41869815f782a2ea1178bdea006e3a7587441323 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-09intel/i440bx: Correct RAM init programmingKeith Hui
Corrects MBSC/MBFS programming when initializing DRAM on boards with both 3 and 4 DIMM slots. Reformats comments to current coreboot standards. Drops some romcc "optimizations" no longer necessary. Boot tested on asus/p2b-ls, where it fixes a memory related hang after SeaBIOS resets the board with nothing to boot from. Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-30vx900/chrome9hd: fix a trivial typoLubomir Rintel
Change-Id: Ibfe6a6dc63454deacfd12de6dad2d6a792474f55 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-30intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)Elyes HAOUAS
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-03nb/intel/gm45: Enable LAPIC monotonic timerNico Huber
Change-Id: I9f96561120d0feb44c5edd9e7241bc3456b31e5f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-29nb/intel/i3100: Don't select UDELAY_IOArthur Heymans
This partially reverts 2510e2aa "northbridge/intel/i3100: Unify UDELAY selection" which moved all supported boards from UDELAY_TSC to UDELAY_IO. Since UDELAY_IO is the default this changes nothing. Change-Id: I42856e5929a7ba047987414a25cd0ae9712434a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22173 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-283rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber
Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28drivers/intel/gma: Put gma_gfxinit() into its own headerNico Huber
The current header `i915.h` is too invasive to be used everywhere where we want to use *libgfxinit*. Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-22nb/intel/pineview: Port ACPI opregion to pineviewPatrick Rudolph
Port the ACPI opregion implementation that resides in drivers/intel/gma to older platforms. It allows to include a vbt.bin and allows GNU/Linux to load the opregion as ASLB is being set. Windows' Intel will likely ignore it as it relies on legacy VBIOS to be loaded at 0xc0000. Change-Id: Ifc9fc52d84dcbb0da577e61467ece8a48752f44b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19nb/sandybridge: Add a kconfig option to ignore XMP max DIMMsVagiz Trakhanov
XMP profiles can have a restriction on max supported DIMMs per channel, but many configurations work with more DIMMs. This is relevant on mainboards with 2 DIMM slots per channel (usually 4 in total). Populating both slots with DIMMs that support XMP profiles only with 1 DIMM per channel turns off said XMP profiles. TEST=On a system with two DIMM slots per channel populate both slots on one channel and ensure that DIMMs run with XMP profiles enabled. Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3 Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-16sandybridge/acpi: remove unnessary check of PCI IDsVagiz Trakhanov
DRAM Controller is always 00.0. No need to check its PCI ID. Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-16nb/intel: Add Ivy Bridge Server (Xeon-E3v2) PCI IDsVagiz Trakhanov
Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-13nb/intel/*/gma: Port ACPI opregion to older platformsPatrick Rudolph
Port the ACPI opregion implementation that resides in drivers/intel/gma to older platforms. It allows to include a vbt.bin and allows GNU/Linux to load the opregion as ASLS is being set. Windows' Intel will likely ignore it as it relies on legacy VBIOS to be loaded at 0xc0000. Tested successfully on DG43GT (x4x) with vbt.bin, with X200 (gm45) with vendor option rom and D945GCLF (i945) with fake vbt. Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-12nb/intel/sandybridge/raminit: Fix setting scramble seed for CH1Arthur Heymans
The scramble seed intended for CH1 were written to the regs of CH0. Write the scramble seed for CH1 at the correct offset. TESTED on Lenovo T430, HP 2760P, Asrock B75PRO3-M. Change-Id: I3778947e96b3298c38e6d5b74988e617e1ffea7b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2017-10-06AGESA f16kb: Enable MRC cache equivalent fastbootKyösti Mälkki
Try restoring previous memory training results from SPI flash to improve raminit speed. Change-Id: I6f4c2342e2eea6c1ecfb71da8564225b6230f51e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03nb/intel/gm45: Remove UMA alignment optimizationNico Huber
This code path was only triggered in one corner case: GFX UMA set to 48MiB. It created a hole below UMA to save MTRRs. But, this hole was never accounted for when calculating cbmem_top(). Instead of trying to fix it, remove it, it's not worth the trouble. TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings. Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-03nb/intel/sandybridge: Refactor dram_dimm_mapping()Nico Huber
Remove no-op statements and code-rephrasing comments, apply some cosmetic changes to improve readability. Change-Id: I124a6bc338c2589fab66ca91bf53139b4413d10b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-29AGESA binaryPI: Drop amdlib.h in dimmSpd.hKyösti Mälkki
Change-Id: Ic1713d1530071e29bd04b525f68d4a44d20ea2e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-27nb/intel/sandybridge/raminit: Improve readabilityPatrick Rudolph
Add debug messages for SPD probing. Change-Id: I722102b7981781b88cdc4877f698294eb719ff32 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-26AGESA: Move API interface under drivers/Kyösti Mälkki
New AGESA support files will be used for binaryPI platforms as well. Furthermore, some of those should move from split nb/ sb/ directories to soc/, so move support files for the API under drivers/. Change-Id: I549788091de91f61de8b9adc223d52ffb5732235 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA: Implement POSTCAR_STAGEKyösti Mälkki
Move all boards that have moved away from AGESA_LEGACY_WRAPPER or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE. We use POSTCAR_STAGE as a conditional in CAR teardown to tell our MTRR setup is prepared such that invalidation without writeback is a valid operation. Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA: Drop unused code in eventlogKyösti Mälkki
Change-Id: I1d4b86c0e74cf4e1a7862889638125e5adcd4c3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26binaryPI: Drop Options.h includeKyösti Mälkki
Change-Id: Ide14bd164fe4a1846f86c6be326e2cd4f540bf97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26AGESA: Avoid cpuRegisters.h includeKyösti Mälkki
Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA cimx: Move cb_types.h to vendorcodeKyösti Mälkki
This file mostly mimics Porting.h and should be removed. For now, move it and use it consistently with incorrect form as #include "cbtypes.h". Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-25nb/i945/raminit: Don't fall back to smbus read on failed SPD decodeArthur Heymans
SPD decoding problems are no longer a good method for detecting if i2c byte read failed, since the return value of i2c_block_read is checked. Change-Id: I230aa22964c452cf28a9370c927b82c57e39cc62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 02:00:10 +0000