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2013-06-13AMD: Kconfig cleanupKyösti Mälkki
Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3433 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-10VX900: Use MIN/MAX from stdlib.h instead of redefining themAlexandru Gagniuc
Change-Id: I2dd693b300085493baa65bb652df8d6cce80b63b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3431 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-10VIA VX900: Add minimal ramstage needed to boot linuxAlexandru Gagniuc
This is the minimal code needed to get past ramstage, load SeaBIOS, jump to GRUB2, and boot linux (or load memtest). See individual source files for the status of each individual component. Change-Id: Ib7d5d7593c945f18af2c2fc5e0ae689ba66131a2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3419 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VX900: Add DDR3 initializationAlexandru Gagniuc
The VX900 can be connected to either DDR2 or DDR3. On my board, it is DDR3, hence why there is no and will be no DDR2 code from my side. This is the raminit for DDR3 dimms for the VX900. I like the term "raminit" better than "memory training". This is a device, not a dog. What works and what doesn't is documented in the code. It does not make sense to hide that information in a commit message. Change-Id: Ib2ebc10e6d4d22d0a937fe9e895c17ce79153c88 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3417 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VX900: Add support for early romstageAlexandru Gagniuc
Add support for VX900 early initialization up until, but not including raminit. Add the basic infrastructure, add a romstrap table, and functionality to configure the CPU bus and SMBus. This code is necessary and sufficient to prepare us for raminit. Change-Id: Icc9c41e4927b589f17416836f87a6a5843b24aa7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3372 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-07i945: Add Display defines for int15h handler.Denis 'GNUtoo' Carikli
Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3306 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-05Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGSDenis 'GNUtoo' Carikli
X86EMU_DEBUG_TIMING is needed for producing i915tool compatible output. So add its dependencies to the i945’s Kconfig in order to be able to use X86EMU_DEBUG_TIMINGS, which depends on HAVE_MONOTONIC_TIMER which LAPIC_MONOTONIC_TIMER provides/selects. Note that UDELAY_LAPIC is already selected by the Intel CPU. Change-Id: Ie834ebc92e527eb186a92b39341ebd0a08889fb0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3356 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architectureRonald G. Minnich
The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer since it was defined in sandybridge. It is really more of an x86 thing however, and we now have three systems that can use it. I considered making this more general, since it technically can apply to PTE-based systems like ARM, and maybe we should. But the 'WRCOMB' moniker is usually closely tied to the x86. Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3349 Tested-by: build bot (Jenkins)
2013-06-04AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"Christian Gmeiner
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: convert spd_read_byte() to non-static versionChristian Gmeiner
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3369 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: rename get_systop() to get_top_of_ram()Christian Gmeiner
Change-Id: I6126d575b8289f76b38858304836e3037200bcdb Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3367 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: include northbridge.h in raminit.cChristian Gmeiner
Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3365 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-staticChristian Gmeiner
Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3364 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: add some missing includesChristian Gmeiner
This commit fixes problems if we build raminit.c for romstage. Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3363 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: make sdram_* function prototypes non-staticChristian Gmeiner
In order to get rid of the bad #include "northbridge/amd/lx/raminit.c" line we need to do some prepartion steps. This commit is one of them. Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3362 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Fam 15tn: Use all memory on systems with more than 4 GBSiyuan Wang
Take a Parmer board with 4G memory as an example. Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'. Parmer uses 512M as video memory when it has 4G. 3327540+512*1024 = 3851828(kB), so some memory is lost. When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is 0x00000001. But in e820 table or coreboot table, the last item is 6: 0000000100000000 - 0000000118000000 = 1 RAM This is not correct, it should be 6: 0000000100000000 - 000000011f000000 = 1 RAM This patch changes the memory layout when TOM2 is set. Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3366 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03haswell: fix overflow handling TOUUDAaron Durbin
It's possible that the TOUUD can be set to less than 4GiB. When that is the case the size_k variable is an extremely large value. Instead ensure TOUUD is greater than 4GiB before adding said resources. Change-Id: I456633d6210824e60665281538300fd15656b86d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3352 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03northbridge/amd/amdmct: Use `static const` instead of `const static`Paul Menzel
From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. The following command was used to make the change. $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/' As asked by Bruce Griffith, the changes in `src/vendorcode` were reverted as that is what AMD prefers. The same change was done already for AMD Persimmon in the following commit. commit 824e192809e021b3cdee947a44b3a18d276bdb35 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` Reviewed-on: http://review.coreboot.org/2474 Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3197 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-05-25Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`Ronald G. Minnich
multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it. Per secunet, no copyright notice is needed. This might be a good time to get a copyright notice into tsc.h anyway. Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3242 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-23Intel Sandy Bridge: udelay.c: Change comparison from <= to <Paul Menzel
Currently code in `udelay.c` differs between the Intel northbridges GM45, 945 on the one hand and Sandy Bridge on the other hand. The reason for this is that a wrong comparison > was used. The following commit commit 784ffb3db694dd2c964d9a4e1c6657a835b2d141 Author: Sven Schnelle <svens@stackframe.org> Date: Tue Jan 10 12:16:38 2012 +0100 i945: fix tsc udelay() Reviewed-on: http://review.coreboot.org/530 fixed the sign from > to <, whereas Stefan Reinauer changed it from > to <= before adding the Sandy Bridge port in the following commit. commit 00636b0daefc3c499990744226a0e1a316d71731 Author: Stefan Reinauer <stefan.reinauer@coreboot.org> Date: Wed Apr 4 00:08:51 2012 +0200 Add support for Intel Sandybridge CPU (northbridge part) Reviewed-on: http://review.coreboot.org/854 As there are no technical reasons for this difference, unify this between the chipsets. See the discussion of the other patch set in Gerrit [1]. [1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3259 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-05-22intel/gm45: Add more debug output to read/write trainingNico Huber
Add debug output for the timing values of the edges found during read and write training. Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like: [...] Lower bound for byte lane 0 on channel 0: 0.0 Upper bound for byte lane 0 on channel 0: 8.4 Final timings for byte lane 0 on channel 0: 4.2 Lower bound for byte lane 1 on channel 0: 0.0 Upper bound for byte lane 1 on channel 0: 10.2 Final timings for byte lane 1 on channel 0: 5.1 Lower bound for byte lane 2 on channel 0: 0.0 Upper bound for byte lane 2 on channel 0: 7.5 Final timings for byte lane 2 on channel 0: 3.6 Lower bound for byte lane 3 on channel 0: 0.0 Upper bound for byte lane 3 on channel 0: 11.4 Final timings for byte lane 3 on channel 0: 5.6 Lower bound for byte lane 4 on channel 0: 0.0 Upper bound for byte lane 4 on channel 0: 9.4 Final timings for byte lane 4 on channel 0: 4.6 Lower bound for byte lane 5 on channel 0: 0.0 Upper bound for byte lane 5 on channel 0: 11.2 Final timings for byte lane 5 on channel 0: 5.5 Lower bound for byte lane 6 on channel 0: 0.0 Upper bound for byte lane 6 on channel 0: 8.4 Final timings for byte lane 6 on channel 0: 4.2 Lower bound for byte lane 7 on channel 0: 0.0 Upper bound for byte lane 7 on channel 0: 10.4 Final timings for byte lane 7 on channel 0: 5.2 Lower bound for group 0 on channel 0: 1.7.5 Upper bound for group 0 on channel 0: 2.2.2 Final timings for group 0 on channel 0: 1.10.7 Lower bound for group 1 on channel 0: 1.6.1 Upper bound for group 1 on channel 0: 2.0.2 Final timings for group 1 on channel 0: 1.9.1 Lower bound for group 2 on channel 0: 2.0.7 Upper bound for group 2 on channel 0: 2.8.1 Final timings for group 2 on channel 0: 2.4.4 Lower bound for group 3 on channel 0: 2.4.7 Upper bound for group 3 on channel 0: 3.0.0 Final timings for group 3 on channel 0: 2.8.3 [...] Final timings are always the average of the two bounds. The last dots separate eights (not decimals) and the middles are elenvenths or twelfths depending on the clock speed (twelfths in this case). Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22intel/gm45: Handle overflows during DDR3 write trainingNico Huber
We halted the machine on any overflow during the write training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3256 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22intel/gm45: Refactor DDR3 write trainingNico Huber
Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3255 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22intel/gm45: Handle overflows during DDR3 read trainingNico Huber
We halted the machine on any overflow during the read training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I77085840ade25bce955480689c84603334113d1f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22intel/gm45: Refactor DDR3 read trainingNico Huber
Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3253 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22intel/gm45: Fix interpretation of VT-d disable bitNico Huber
When configuring the GTT size for the integrated graphics, the state of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is _disabled_. In the log of a VT-d enabled roda/rk9 we have now: [...] VT-d enabled [...] IGD decoded, subtracting 32M UMA and 4M GTT [...] Without this patch, only 2M GTT were reported. Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3252 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-21intel/i5000: Remove unused copy of udelay.cNico Huber
It's a copy from i945 and looks like not beeing included in a build at all. If you should ever want to use that file for the Intel 5000, please copy it from another chipset like the Intel 945 as it is going to be improved. Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a Reported-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3219 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10Get rid of a number of __GNUC__ checksStefan Reinauer
In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3226 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-10northbridge/intel/i5000/udelay.c: Remove unused header `console.h`Paul Menzel
Nothing from the header `console.h` is needed in `udelay.c`, so do not include it. This header was included since commit »Add Intel i5000 Memory Controller Hub« (17670866) [1]. [1] http://review.coreboot.org/491 Change-Id: Ie136a1b862b55c9471f9293ed616ce27a1d01a50 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3218 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10Drop prototype guarding for romccStefan Reinauer
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-08Drop CONFIG_AP_CODE_IN_CARStefan Reinauer
This option has not been enabled on any board and was considered obsolete last time it was touched. If we need the functionality, let's fix this in a generic way instead of a K8 specific way. This was mostly a speedup hack back in the day. Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3211 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-08hardwaremain: drop boot_complete parameterStefan Reinauer
it has been unused since 9 years or so, hence drop it. Change-Id: I0706feb7b3f2ada8ecb92176a94f6a8df53eaaa1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3212 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-07haswell: use tsc for udelay()Aaron Durbin
Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3169 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01boot: remove cbmem_post_handling()Aaron Durbin
The cbmem_post_handling() function was implemented by 2 chipsets in order to save memory configuration in flash. Convert both of these chipsets to use the boot state machine callbacks to perform the saving of the memory configuration. Change-Id: I697e5c946281b85a71d8533437802d7913135af3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3137 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18Intel i945: ACPI: Add _OSC methodDenis 'GNUtoo' Carikli
Add the ACPI Operating System Capabilities Method and let the operation system control everything. Commit »AMD Fam14 DSDT: Add OSC method« (00a0e76b) [1] is used as a template. The Lenovo X60 [2] running the Parabola GNU/Linux distribution [3] is used for testing. Before that change: $ dmesg | egrep -e OSC -e ASPM [ 0.108036] pci_root PNP0A08:00: ACPI _OSC support notification failed, disabling PCIe ASPM [ 0.108040] pci_root PNP0A08:00: Unable to request _OSC control (_OSC support mask: 0x08) [ 0.118089] ACPI _OSC control for PCIe not granted, disabling ASPM [ 16.874569] e1000e 0000:01:00.0: Disabling ASPM L0s L1 With that change: $ dmesg | egrep -e OSC -e ASPM [ 0.107962] pci_root PNP0A08:00: Requesting ACPI _OSC control (0x1d) [ 0.108003] pci_root PNP0A08:00: ACPI _OSC control (0x1d) granted [ 0.111052] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' [ 17.537970] e1000e 0000:01:00.0: Disabling ASPM L0s L1 [1] http://review.coreboot.org/2738 [2] http://www.coreboot.org/Lenovo_x60x [3] https://parabolagnulinux.org/ Change-Id: I1caffa44eea447d553c01caaf431f2db241ea5ea Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2938 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16Lenovo ThinkPad X60: Add Native VGA init.Denis 'GNUtoo' Carikli
The code has been taken from the google link mainboard and modified to fit the ThinkPad X60. Change-Id: Ie16e45163acdc651ea46699ecc33055bfd34099c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/2998 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-12Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"Nico Huber
This reverts commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5: commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5 Author: Patrick Georgi <patrick.georgi@secunet.com> Date: Tue Apr 9 15:41:23 2013 +0200 siemens/sitemp_g1p1: Make ACPI report the right mmconf region ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> It sneaked in without it's dependencies and, therefore, broke the build for all amdk8 targets. Paul Menzel already commented on the issue in [1]. It also doesn't look like the dependencies would be pulled soon [2]. [1] http://review.coreboot.org/#/c/3047/ [2] http://review.coreboot.org/#/c/2662/ Change-Id: Ica89563aae4af3f0f35cacfe37fb608782329523 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3063 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-04-11Persimmon/Fam14/SB800 DSDT: Split into common areasMike Loptien
Split the Persimmon DSDT into common code areas. For example, split the Southbridge specific code into the Southbridge directory and CPU specific code into the CPU directory. Also adding the superio.asl file to the Persimmon DSDT tree. This file is empty for the moment but will be necessary in the future. I have also emptied the thermal.asl file in the mainboard directory because it does not seem to perform as intended (fan control does not change when it is brought back into the code base) and it has been inside a '#if 0' statement for a long time. Removing it until it is decided that it is actually necessary. This change was verified in three different ways: 1. Visual comparison of the compiled DSDT pulled from the Persimmon after booting into Linux using the ACPI tools acpidump, acpixtract, and iasl. The comparison was done between the DSDT before and after doing the split work. This test is somewhat difficult considering the expanse of the changes. Blocks of code have been moved, and others changed. 2. Linux logs were dumped before and after the DSDT split. Logs dumped and compared include dmesg and lspci -tv. Neither log changed significantly between the two compare points. 3. The test suite FWTS was run on the Coreboot build both before and after doing the DSDT split with the command 'sudo fwts -b -P -u'. The flag -b specifies all batch jobs, -P specifies all power tests, and -u specifies utilities. Interactive jobs were not run as most of them consist of laptop checks. Again, there were no significant changes between the two endpoints. These tests lead me to believe that there was no change in the functionality of the ACPI tables apart from what is known and expected. This patch is the first of a series of patches to split the DSDT. The ASRock patch was merged before this one and breaks the ASROCK E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/). Please be aware of this dependency when pulling these patches. Other patches that depend on this patch are 'AMD Fam14: Split out the AMD Fam14 DSDT' (http://review.coreboot.org/#/c/3051/) and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC' (http://review.coreboot.org/#/c/3052/) Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-10siemens/sitemp_g1p1: Make ACPI report the right mmconf regionPatrick Georgi
ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-04AMD GX1: Remove useless copied header file `northbridge.h`Paul Menzel
This was there since the beginning commit d24d6993b6d7bcf7977d74d081e718e1b076d1b0 Author: arch import user (historical) <svn@openbios.org> Date: Wed Jul 6 17:06:46 2005 +0000 Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26 Creator: Hamish Guthrie <hamish@prodigi.ch> Added AMD GX1 northbridge and cs5530 Southbridge but blindly copied from Intel 440 BX and is not used anywhere. Thanks to Idwer Vollering for spotting this. Change-Id: I38b3d3feb25966c3aa382994d323e59c3f3c9e6c Reported-by: Idwer Vollering Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3020 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2013-04-03sandybridge: enable ROM cachingAaron Durbin
If ROM caching is selected the sandybridge chipset code will will enable ROM caching after all other CPU threads are brought up. Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29sandybridge: add option to mark graphics memory write-combining.Aaron Durbin
The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29haswell: add option to mark graphics memory write-combining.Aaron Durbin
The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I797fcd9f0dfb074f9e45476773acbfe614eb4b0a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29x86: add new mtrr implementationAaron Durbin
The old MTRR code had issues using too many variable MTRRs depending on the physical address space layout dictated by the device resources. This new implementation calculates the default MTRR type by comparing the number of variable MTRRs used for each type. This avoids the need for IORESOURE_UMA_FB because in many of those situations setting the default type to WB frees up the variable MTTRs to set that space to UC. Additionally, it removes the need for IORESOURCE_IGNORE_MTRR becuase the new mtrr uses the memrange library which does merging of resources. Lastly, the sandybridge gma has its speedup optimization removed for the graphics memory by writing a pre-determined MTRR index. That will be fixed in an upcoming patch once write-combining support is added to the resources. Slight differences from previous MTRR code: - The number of reserved OS MTRRs is not a hard limit. It's now advisory as PAT can be used by the OS to setup the regions to the caching policy desired. - The memory types are calculated once by the first CPU to run the code. After that all other CPUs use that value. - CONFIG_CACHE_ROM support was dropped. It will be added back in its own change. A pathological case that was previously fixed by changing vendor code to adjust the IO hole location looked like the following: MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 As noted by the output below it's impossible to accomodate those ranges even with 10 variable MTRRS. However, because the code can select WB as the default MTRR type it can be done in 6 MTRRs: MTRR: default type WB/UC MTRR counts: 6/14. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23resources: introduce reserved_ram_resource()Aaron Durbin
mmio_resource() was previously being used for reserving RAM from the OS by using IORESOURCE_IGNORE_MTRR atrribute. Instead, be more explicit for those uses with reserved_ram_resource(). bad_ram_resource() now calls reserved_ram_resource(). Those resources are marked as cacheable but reserved. The sandybridge and haswell code were relying on the implementation fo the MTRR algorithm's interaction for reserved regions. Instead be explicit about what ranges are MMIO reserved and what are RAM reserved. Change-Id: I1e47026970fb37c0305e4d49a12c98b0cdd1abe5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2886 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22haswell: use dynamic cbmemAaron Durbin
Convert the existing haswell code to support reloctable ramstage to use dynamic cbmem. This patch always selects DYNAMIC_CBMEM as this option is a hard requirement for relocatable ramstage. Aside from converting a few new API calls, a cbmem_top() implementation is added which is defined to be at the begining of the TSEG region. Also, use the dynamic cbmem library for allocating a stack in ram for romstage after CAR is torn down. Utilizing dynamic cbmem does mean that the cmem field in the gnvs chromeos acpi table is now 0. Also, the memconsole driver in the kernel won't be able to find the memconsole because the cbmem structure changed. Change-Id: I7cf98d15b97ad82abacfb36ec37b004ce4605c38 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2850 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22coreboot: dynamic cbmem requirementAaron Durbin
Dynamic cbmem is now a requirement for relocatable ramstage. This patch replaces the reserve_* fields in the romstage_handoff structure by using the dynamic cbmem library. The haswell code is not moved over in this commit, but it should be safe because there is a hard requirement for DYNAMIC_CBMEM when using a reloctable ramstage. Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell/lynxpoint: Use new PCH/PM helper functionsDuncan Laurie
This makes use of the new functions from pmutil.c that take care of the differences between -H and -LP chipsets. It also adds support for the LynxPoint-LP GPE0 register block and the SMI/SCI routing differences. The FADT is updated to report the new 256 byte GPE0 block on wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address block so that part is zeroed to prevent IASL and the kernel from complaining about a mismatch. This was tested on WTM2. Unfortunately I am still unable to get an SCI delivered from the EC but I suspect that is due to a magic command needed to put the EC in ACPI mode. Instead I verified that all of the power management and GPIO registers were set to expected values. I also tested transitions into S3 and S5 from both the kernel and by pressing the power button at the developer mode screen and they all function as expected. Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2816 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell: Drop the device ID check in graphics init pathDuncan Laurie
Change-Id: I10c4264d317b5fac02a44f50ed10b457e1865e17 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2809 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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