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2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
It looks like this hardware has a bug where the display controller does not work properly when dram is clocked 533MHz and the channels are configured in non-stacked mode. The workaround is to select stacked mode in this configuration. Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
There seems to be a hardware bug where the combination of non-stacked channel settings, both channels populated and 533MHz dram speed cause the display to be unusable. The code to actually select stacked mode based on hardware configuration will be add in a followup patch. This patch does the following: * Add option to the sysinfo struct for stacked mode * Fix programming channel 1 DRB which needs special care for the last populated rank in stacked mode TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz) Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14AGESA binaryPI: Drop RAMBASE and RAMTOPKyösti Mälkki
With platforms moved to RELOCATABLE_RAMSTAGE, these overrides no longer have a meaning. Overrides existed because AGESA ramstage did not fit within the default 1 MiB of RAMTOP - RAMBASE, when placed low. Change-Id: I0185875dc550de74877c94f36128d5979e5553d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26813 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
Change-Id: Ia637d32ffaa5d280320955d34141eddc8b7df981 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22222 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
This adds a common function to decode the TSEG size from the ESMRAM register. This will come in handy when SMM in TSEG is implemented. This function is used both in romstage and in ramstage. Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23448 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06intel/e7505: Remove ROMCC workaroundKyösti Mälkki
Choose codepath as if ROMCC_IF_BUG_FIXED was set. Change-Id: I74b4fe4a915b70f63ea018035381b64f53af3c7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki
To flip the Kconfig default, flag some platforms with NO_RELOCATABLE_RAMSTAGE. Change-Id: I72c6d07e5a60789bbe0e068a0130d7e3bd07a1d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05northbridge/amd/lx: Fix function setShadowRCONFIru Cai
GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical `&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise `&`. Also fix off-by-one error with the bitmasks. Change-Id: I7d7720121d4730254542372282f5561739e7214b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20808 Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05amd/geode_lx: Fix .c includesKyösti Mälkki
Change-Id: I2cce52561d30e30e1c81752cd2a455e7211006eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2018-06-05cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans
Tested on Google Peppy (Acer C720). Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26793 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans
Also removes some non-POSTCAR_STAGE functions, since those are unused now. Change-Id: I439bffbe39411186355d374eed7d5efd63fb02e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26792 Reviewed-by: Matthias Gazzari <mail@qtux.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans
Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin. Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05nb/intel/gm45: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26788 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05nb/intel/pineview: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05nb/intel/i945: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04intel/i440bx: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Change-Id: I08c28862cc66956bdcab6ac9362b3d50bb64e78f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04nb/via/vx900: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I31143e1c7f1c52dec9673f75d73031632049ddbf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26529 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-02intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGEKyösti Mälkki
Change-Id: Ie522e8fda1d6e80cc45c990ff19a5050165d8030 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-02intel/e7505: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: Icc4cef468ede2c1db052850efd155b626e392dae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26744 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-02intel/e7505: Assume AGP slot disabledKyösti Mälkki
Reducing two AGP aperture windows from default 256 MiB to chipset minimum 4 MiB releases 504 MiB of unused MMIO space. Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB. Supported CPUs are 32-bit with PAE, so there is a little reason to avoid overlarge MMIO region. Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki
With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02intel/e7505: Fix domain resourcesKyösti Mälkki
Fixed resources have to be registered early during read_resources() phase, such that device allocator will avoid them. Change-Id: I3c120cfb96c185f0052b9b3cdd93eeed0f712491 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-31Remove VIA VX800 northbridge supportKyösti Mälkki
Change-Id: Id6026e9d7ff064d54b0dd93e80dabdcc4efd2b8e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove VIA CX700 northbridge supportKyösti Mälkki
Change-Id: Id46e3d40393598f6b03ae4fd3186182635f072ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove VIA CN700 northbridge supportKyösti Mälkki
Change-Id: I6c33d35718cc445ce67fc625d71420ded3828d8b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove AMD K8 cpu and northbridge supportKyösti Mälkki
Change-Id: I9c53dfa93bf906334f5c80e4525a1c27153656a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31Remove southbridges after K8 board removalsKyösti Mälkki
Change-Id: Ib6935c026e2302b037fc82be64163f10bf775751 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31Remove all AMD K8 boardsKyösti Mälkki
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-29src/northbridge: Add and update license headersMartin Roth
This change adds and updates headers in all of the northbridge files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all northbridge directories. Change-Id: I8cd7c04ddb8e58946dcdf9c7c125e23698647a73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-24nb/intel/fsp_sandybridge: Fix lost const qualifier on 'device_t'Elyes HAOUAS
Missing '*const' in Change #26195 added into function northbridge_get_tseg_base(void). Change-Id: Ideb9a9cb98d34f2ed1034b8ee20b3b06aa5ff1e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26455 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24AMD geode/lx: Remove generic_sdram.c includeKyösti Mälkki
The file under lib/ will be removed with K8 and Geode LX is the only other platform using it. Change-Id: Id49d72358ecfc4aae4980e3ae787952073e5c838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24Remove leftover AMD CIMX RD890 northbridge supportKyösti Mälkki
Change-Id: I3f2cea79a11a52e94f479b25f22eb3726af38fa3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24nb/amd/amdfam10: Get rid of device_tKyösti Mälkki
Change-Id: Iac6be374842063cc383af20c73900e3699a72653 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
When programming the final dram attribute and dram boundary settings, on DDR3 dram one also needs to enable ZQCAL in the CxREFRCTRL (DRAM Refresh Control) register as documented in "Intel ® 4 Series Chipset Family" documentation. Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
DDR3 adapted a fly-by topology which allows for better signal integrity but at the same time requires additional calibration. This is done by settings the targeted rank in write leveling mode while disabling output buffer on the other ranks. After that the DQS signal gets sampled over DQ until a transition from high to low is found. Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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