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2017-08-28AGESA: Remove Kconfig AMD_AGESA_FAMILY10Kyösti Mälkki
Never selected in our tree. The vendorcode source for fam15 also includes fam10 support if required. Change-Id: Ifff328ecdd8afa988f844b6fd631818b51bd5b5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28AGESA f15: Remove f10 referencesKyösti Mälkki
Vendorcode for f15 also has f10 support, so AMD_AGESA_FAMILY_10 was never selected. Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-27nb/intel/pineview: Fix typo in DRAM timing computationArthur Heymans
This problem was introduced in: 12a4e98cea nb/intel/pineview/raminit: Refactor timings selection Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-24AGESA: Sync f15tn and f15rl northbridge codeKyösti Mälkki
Change-Id: Ia55c82f2245335a5d02e4d6567f606596c8439c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-08-22AMD K8 fam10-15: Tidy up CAR disableKyösti Mälkki
Avoid conflicting disable_cache_as_ram() declaration and tidy up include for inlined function. Change-Id: Iba77c711f5eb023566b7d8ba148583948661bc99 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-20nb/intel/x4x: Fix booting with FSB800 DDR667 combinationArthur Heymans
A small typo in the dll setting code prevented this combination from booting. TESTED on ga-g41m-es2l with 800MHz FSB CPU and 667MHz ddr2 Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-20nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans
Moves receive enable calibration to a separate file to lighten raminit.c a bit. Receive enable calibration is quite similar to gm45 so it reuses some of its function names. The functional changes are: * the minimum coarse is now reset for each channel; * on the second fine search for DQS high, TAP overflow is handled by increasing medium; * start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges do the same and the results are more in line with register dumps from vendor bios. These might improve stability. TESTED on ga-g41m-es2l Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-18nb/intel/i440bx: Compile debug.c only if CONFIG_DEBUG_RAM_SETUPKeith Hui
... is enabled. Otherwise we are compiling an effectively empty file. Change-Id: I4e3d982066d1fa66a3da5f37e278ec7fd5bb1ea8 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2017-08-16AGESA: Cleanup ACPI S3 supportKyösti Mälkki
Due to low-memory corruptions S3 support has now been (at least temporarily) removed from AGESA platfroms. Should we bring it back one day, CAR teardown on S3 path will happen with an empty stack so ugly backup/recovery of the stack will no longer be used. If S3 feature is brought back, resume path code for FCH will also see partial rewrite and agesawrapper.c file will not be part of that. Change-Id: Ib38c04d0e74f600e0b719940d5e2530f4c726cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-16AGESA f14: Sacrifice ACPI S3 support for EARLY_CBMEM_INITKyösti Mälkki
A decision has been made that boards with LATE_CBMEM_INIT will be dropped from coreboot master starting with next release scheduled for October 2017. As existing implementation of CAR teardown in AGESA can only do either EARLY_CBMEM_INIT or ACPI S3 support, choose the former. ACPI S3 support may be brought back at a later date for these platforms but that requires fair amount of work fixing the MTRR issues causing low-memory corruptions. Change-Id: I5d21cf6cbe02ded67566d37651c2062b436739a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-14nb/intel/sandybridge/gma: Fix S3 resumePatrick Rudolph
The S3 resume path is broken on current Linux (4.11.3) and maybe on older kernel, too. Don't run the native graphics init when on S3 resume to fix it. Tested on Lenovo T430. Change-Id: Ifad145c86c2e8f019c507f97c889b70b7aa49882 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-11nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I portsArthur Heymans
This allows the use of the native VGA init on boards featuring DVI-I ports. Digital output is not supported. Change-Id: I11a4dd68746e06c7e27ecf3e765bdd0d8cf40515 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-11drivers/intel/gma/opregion: migrate from nb/commonMatt DeVillier
Migrate opregion code from northbridge/intel/common to drivers/intel/gma in preparation for consolidation with soc/intel/common opregion code. Rename init_igd_opregion() for clarity and disambiguation with other implementations. Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-10nb/intel/sandybridge/raminit: Add Kconfig option for fusesPatrick Rudolph
Add a new Kconfig option to ignore memory fuses that limit the maximum DRAM frequency to be used. The option is disabled by default and should only enabled by experienced users as it might decrease system stability or prevent a successful RAM training. Remove conflicting devicetree settings. Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nicola Corna <nicola@corna.info>
2017-08-10nb/amd_fam10/mct_ddr3: Use common function to compute crc16 checksumArthur Heymans
Change-Id: I730a8a150134cc1ef8fb3872728bb0586ac7b210 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19732 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-08-07nb/intel/*/gma.c: Use macros for GMBUS numbersArthur Heymans
Change-Id: I885b6bd9f5be6b4e3696a530016123a3e81c4b10 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-06sb/intel/*: Use common SMBus functionsArthur Heymans
All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-02binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Add dispatcher for PI blobKyösti Mälkki
Change-Id: I622d155fce3fa56cd5e24282e22de060fed560c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA f15tn f16kb: Implement common FCH calloutKyösti Mälkki
This FCH_OEM_CALLOUT bypasses API and uses structures that are private to AGESA. Attempt to clean it up by first clarifying when it is used. Change-Id: I63aa0f586f73e97d615b8596d73728edbaeb0a2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I0c0058be002e409bd16d2d75fd404df94407df4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Enable EARLY_CBMEM_INITKyösti Mälkki
Also moves postcar stack to CBMEM. Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19347 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02AGESA: Conditionally enable RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: Id199322db077fc5f112dfa45f8e9f72b9142a8fb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Implement EARLY_CBMEM_INITKyösti Mälkki
Boards without AGESA_LEGACY_WRAPPER gain EARLY_CBMEM_INIT. This does not apply to family12 and family14 just yet, as they do invalidate without write-back on CAR teardown. Change-Id: I008356efa2bc3df0ed1f0720e225ecc7e9995127 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Split dispatcher to stagesKyösti Mälkki
Change-Id: Ide49e46c0b6aa5e1bf09354435a847a46bc797c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Move romstage-ramstage splitlineKyösti Mälkki
In AGESA specification AmdInitEnv() is to be called once host memory allocator has started. In coreboot context this could mean either availability of CBMEM or malloc heap. As for AmdS3LateRestore(), there is no requirement to have it run as part of the romstage either. Change-Id: Icc8d97b82df89e2480e601d5c2e094de0365b0a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA binaryPI: Unify agesawrapper headerKyösti Mälkki
Change-Id: I54c8553bc057798e595b28f6cbc07f7125ae074f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define AGESA_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Move agesawrapper_laterunaptask()Kyösti Mälkki
Change-Id: I916d808d1b2ecc4b70b5dfebff62c4a18119f157 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Refactor eventlog read loopKyösti Mälkki
Also avoid infinite loop. Change-Id: I7571f9efdc2bf0335788136b8c56e9290581d748 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Use common handler for ACPI tablesKyösti Mälkki
Change-Id: I2d6ab1026f1105f1fea97682442a169409248c39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-01src/northbridge: Add guards on all header filesMartin Roth
Change-Id: I93b939478615f22f2c078b1efb7999ad4f3a4c28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-07-30intel/sandybridge: Clean VGA BIOS ids up a littleNico Huber
Sync map_oprom_vendev() and autoport with the list of PCI ids in the `gma.c` driver, remove one obsolete Kconfig default override. Change-Id: I12f24f415b695c516fbb947114e09c873af2e439 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-30intel/sandybridge: Gather MMCONF_BASE_ADDRESS defaultsNico Huber
All affected boards did the same USE_NATIVE_RAMINIT distinction or actually selected USE_NATIVE_RAMINIT. Also update autoport. Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20813 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-07-29binaryPI: Drop remains of ACPI S3 on FCHKyösti Mälkki
Never reached and actual code was already wiped out. Change-Id: Ic17cbc56e83d23e228e23578357843ac9cd77eda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20623 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-24nb/intel/i440bx: Add final newline to raminit.cMartin Roth
The newline lint check just went in, and immediately broke the build due to a commit that went in earlier today. This fixes the build. Change-Id: Ic4ba8ce0c8085861bc6c654afdee3fea9f4621fc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-23northbridge/intel/i440bx: Merge RAM init routinesKeith Hui
There are 4 routines used in RAM init that most if not all i440bx mainboards call in the same order. Implements a single RAM init routine for them to allow for future consolidation. Boards to be changed to use this one routine in a future change. Change-Id: Ib553b07b117de12b7982586bce0f9355f55013a0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-22northbridge/intel/i440bx: Move NB macro to i440bx.hKeith Hui
This move makes the NB macro more widely available, in preparation for implementing get_top_of_ram(). Change-Id: Icd8e82cfdfdccb662b2139d0e5d1d5af72cbae7f Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21nb/intel/x4x: Rework programming DQ and DQS DLL timingsArthur Heymans
This does the following: * Clarify that settings are set to the same value for each rank; * Allows to program coarse * Fix some style issues like white spaces between arithmetic operators. Change-Id: I3a9e28cfec915a0bb15789c23bea259f621b5096 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21nb/intel/pineview/raminit: Refactor timings selectionArthur Heymans
This does not use loops to compute timings but uses DIV_ROUND_UP. Another thing affected by this patch are minimum timings. Presumably those only need to be guarded against on DDR3. With this change timings are set up like vendor (with tWTR below previous minimum) TESTED on Intel D510MO Change-Id: Ia374f26e5bbb8b90d90c24ae6c20412ba53bd7b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21sb/intel/i82801jx: Add correct PCI ids and change namesArthur Heymans
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-17binaryPI: Switch to agesa/def_callouts.cKyösti Mälkki
Change-Id: Id20a49385aeb336461acd0bd186a4ab7f3fb95b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-17binaryPI: Switch to agesa/heapmanager.cKyösti Mälkki
Essentially squashes following commits from AGESA side. 45ff9cb AGESA: Reduce typecasting in heapmanager calls bceccec AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanly 4240277 AGESA: Adjust heap location for S3 resume path 424c639 AGESA: Refactor S3 support functions 50e6daf AGESA: Log heap initialisation da74041 AGESA: Move heap allocator declarations c74b53f AGESA: Reduce SPI use by 24kB for S3 support b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts f728408 AGESA: Split S3 backup in CBMEM 82fbda7 AGESA: Use same HeapManager for all BiosCallOuts Change-Id: I537bd05a3e06ff6896f1ac8be93eed5321ca472b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13AGESA binaryPI: Unify agesawrapper headerKyösti Mälkki
AMD_S3_PARAMS is no longer defined with all binaryPI. Guard these as a build fix to share the header nevertheless. Change-Id: I725ed43991dc1c3e30d236bde4282176819f4cf4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-12nb/intel/sandybridge/gma: Set ASLS on S3 resumePatrick Rudolph
Use new GMA driver method to set ASLS on S3 resume, too. Move gma_enable_swsci to init method as it should always be run. Change-Id: Ic7132cd1848a75043d10f32ac5d0e6b45d2e0fe4 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12nb/intel/haswell/gma: Set ASLS on S3 resumePatrick Rudolph
Use new GMA driver method to set ASLS on S3 resume, too. Move gma_enable_swsci to init method as it should always be run. Change-Id: I1944fcca91ee1a0ad8df5c8b6f402e907de5e78f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12nb/intel/fsp_sandybridge/gma: Set ASLS on S3 resumePatrick Rudolph
Use new GMA driver method to set ASLS on S3 resume, too. Move gma_enable_swsci to init method as it should always be run. Change-Id: I772d680774890c32ca6dc9b1e2143b3ab3bf6513 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12nb/intel/nehalem/gma: Set ASLS on S3 resumePatrick Rudolph
Use new GMA driver method to set ASLS on S3 resume, too. Move gma_enable_swsci to init method as it should always be run. Change-Id: Ifc921d7aa2d5b771fc4eaf3ec776c3a13f5496eb Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12drv/intel/gma/opregion: Add interface for GNVS ASLB handlingPatrick Rudolph
Add and use new interface to set and get GNVS' ASLB register. To be used by Intel's gma driver to set ASLB at ACPI table creation and to get ASLB on S3 resume. Change-Id: If30c6b2270069783b0892774802f47406404da5f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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