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path: root/src/northbridge
AgeCommit message (Expand)Author
2020-09-25nb/intel/x4x/x4x.h: Clean up cosmeticsAngel Pons
2020-09-25nb/intel/x4x/iomap.h: Rename to memmap.hAngel Pons
2020-09-25nb/intel/pineview: Place raminit definitions in raminit.hAngel Pons
2020-09-25nb/intel/gm45/gm45.h: Clean up cosmeticsAngel Pons
2020-09-25nb/intel/gm45: Drop unused `DEFAULT_HECIBAR` macroAngel Pons
2020-09-25nb/intel/gm45: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
2020-09-22nb/intel/ironlake: Use `MSAC` definitionAngel Pons
2020-09-22nb/intel/ironlake: Use DMIBAR/EPBAR macrosAngel Pons
2020-09-21src/northbridge: Drop unneeded empty linesElyes HAOUAS
2020-09-21nb/intel/sandybridge: Check ME status only onceAngel Pons
2020-09-21nb/intel/sandybridge: Simplify SPD validity checkAngel Pons
2020-09-21nb/intel/ironlake: Clean up cosmetics of early ME functionsAngel Pons
2020-09-21nb/intel/ironlake: Clean up `send_heci_uma_message` signatureAngel Pons
2020-09-21nb/intel/ironlake: Reduce the scope of `heci_uma_addr`Angel Pons
2020-09-21nb/intel/sandybridge: Drop unnecessary `gma.h`Angel Pons
2020-09-21nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate filesAngel Pons
2020-09-21nb/intel/sandybridge: Move register headers into a subfolderAngel Pons
2020-09-21nb/intel/sandybridge: Clean up DMIBAR/EPBAR registersAngel Pons
2020-09-21nb/intel/sandybridge: Introduce memmap.hAngel Pons
2020-09-17nb/intel/haswell: Put DMIBAR/EPBAR registers into separate filesAngel Pons
2020-09-17nb/intel/haswell: Move register headers into a subfolderAngel Pons
2020-09-17nb/intel/x4x: Clean up TPM-related codeAngel Pons
2020-09-17nb/intel/pineview: Guard DMIBAR/EPBAR macro parametersAngel Pons
2020-09-17nb/intel/pineview/iomap.h: Rename to memmap.hAngel Pons
2020-09-17nb/intel/ironlake: Do not re-read ME UMA sizeAngel Pons
2020-09-17nb/intel/ironlake: Drop some unused function parametersAngel Pons
2020-09-17nb/intel/ironlake: Drop `heci_bar` field from raminitAngel Pons
2020-09-17nb/intel/haswell: Clean up register definitionsAngel Pons
2020-09-17nb/intel/haswell: Guard DMIBAR/EPBAR macro parametersAngel Pons
2020-09-17nb/intel/haswell: Introduce memmap.hAngel Pons
2020-09-17nb/intel/sandybridge: Drop `void *` cast in `MCHBAR32`Angel Pons
2020-09-17nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
2020-09-17nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
2020-09-17nb/intel/ironlake: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
2020-09-15nb/intel/ironlake/raminit: Work around compiler bugPatrick Rudolph
2020-09-14nb/intel/ironlake: Reserve gap betwen TSEG and BGSMNico Huber
2020-09-14nb/intel/ironlake: Use an `index` variable for resourcesNico Huber
2020-09-08nb/intel/ironlake: Use an enum for `gpu_panel_port_select`Angel Pons
2020-09-08nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`Angel Pons
2020-09-08nb/intel/haswell: Drop `gpu_panel_port_select`Angel Pons
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
2020-08-31nb/intel/sandybridge: Add ECC error injection register informationAngel Pons
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
2020-08-24nb/amd/agesa: define DDR3_SPD_SIZE as a common valueMike Banon
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
2020-08-17nb/amd/agesa: read 256 bytes to SPD buffer instead of 128Mike Banon
2020-08-17src: Use PCI_BASE_ADDRESS_* macros instead of magic numbersElyes HAOUAS
2020-08-17nb/intel/x4x/raminit_ddr23.c: Remove dead assignmentElyes HAOUAS
2020-08-12nb/intel/sandybridge: Add comments to `struct iosav_ssq`Angel Pons
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