coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-11-14	VIA chipsets: fix compilation without real mode code	Stefan Reinauer
2012-11-14	Sandybridge: Set PEG clock gating	Marc Jones
2012-11-14	Add PCIe init and NMode flag to PEI data structure	Stefan Reinauer
2012-11-14	Add ddr3lv_support flag to pei_data structure	Duncan Laurie
2012-11-14	pei_data.h: Fix comment	Marc Jones
2012-11-14	Provide MRC with a console printing callback function	Vadim Bendebury
2012-11-12	Initial IGD OpRegion implementation	Stefan Reinauer
2012-11-12	Avoid using hardcoded values in MRC cache code	Vadim Bendebury
2012-11-09	Make coreboot use the offset parameter in cbfstool create	Stefan Reinauer
2012-11-09	Make register/value lists const	Stefan Reinauer
2012-11-07	SandyBridge/IvyBridge: Use flash map to find MRC cache	Stefan Reinauer
2012-11-07	Add missing newline in error message	Stefan Reinauer
2012-11-07	AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU	Siyuan Wang
2012-11-07	CMOS: Move MRC seed offset into upper bank	Duncan Laurie
2012-11-07	AMD rd890 late.c: Don't enable PCIe ports after PCIe init.	Siyuan Wang
2012-11-07	AMD agesa family15: PCI domain should scan bus from 0x18.0	Siyuan Wang
2012-11-02	Fix some issues with new "reference" toolchain	Stefan Reinauer
2012-10-26	northbridge/sch: move the \n so it reads a little better	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: read the size of main memory from the proper register	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: Read the GPU memory from the correct PCI device	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: don't overwrite hightables with GPU / TSEG memory	Sebastian Andrzej Siewior
2012-10-08	hpet: common ACPI generation	Patrick Georgi
2012-10-07	Remove chip.h files without config structure	Kyösti Mälkki
2012-09-25	HAVE_HIGH_TABLES is gone	Patrick Georgi
2012-09-19	agesa fam15 northbridge: change lapic_id to accommodate two CPUs	Siyuan Wang
2012-08-28	Fix AMD UMA for RS780	Kyösti Mälkki
2012-08-27	AMD northbridges: factor out CPU allocation	Kyösti Mälkki
2012-08-27	AMD northbridges: rewrite CPU allocation	Kyösti Mälkki
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2012-08-09	AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution	Kyösti Mälkki
2012-08-09	Sandybridge: Fix integer overrun in romstage udelay()	Stefan Reinauer
2012-08-08	Cleanup coreboot memory table includes	Kyösti Mälkki
2012-08-07	Move cpus_ready_for_init() to AMD K8	Kyösti Mälkki
2012-08-07	Sandy/Ivy Bridge and Cougar/Panther Point: Fix names	Stefan Reinauer
2012-08-05	AMD f15: Change multiply ONE_MB to bit shifting (Propagation)	zbao
2012-08-04	AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation)	zbao
2012-08-04	AMD NB: Limit the device field to 5 bits. (Propagation)	zbao
2012-08-02	Limit the device field to 5 bits.	zbao
2012-08-02	AMD and GFXUMA: move setup_uma_memory() to northbridge	Kyösti Mälkki
2012-08-02	AMD Agesa and GFXUMA: drop use of uma_memory_base	Kyösti Mälkki
2012-08-02	AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base	Kyösti Mälkki
2012-08-01	AMD F15tn northbridge: Remove the misleading 0x100 from the limitk.	zbao
2012-08-01	Intel and GFXUMA: drop redundant use of lb_add_memory_range()	Kyösti Mälkki
2012-08-01	Intel Sandybridge and UMA: use mmio_resource()	Kyösti Mälkki
2012-08-01	Intel Sandybridge: add reserved memory as resources	Kyösti Mälkki
2012-07-30	sandybridge: reinitialize usbdebug after MRC	Sven Schnelle
2012-07-27	Intel and GFXUMA: fix MTRR and use uma_resource()	Kyösti Mälkki
2012-07-27	Intel 82810 and 82830: always room for PCI memory	Kyösti Mälkki
2012-07-27	Intel i945 and sch: no memory over 4GB	Kyösti Mälkki
2012-07-26	Refactor driver structs	Patrick Georgi