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path: root/src/northbridge
AgeCommit message (Expand)Author
2016-04-20AMD CIMX: Drop unused codeKyösti Mälkki
2016-04-19kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ schemeStefan Reinauer
2016-04-16northbridge/amd/{lx,gx2}: remove immediate accesses of 0Patrick Georgi
2016-04-13amd/agesa/family12/dimmSpd.c: Indent (tab) fixEdward O'Callaghan
2016-04-11and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignmentTimothy Pearson
2016-04-11nb/amd/amdfam10: Write MCT variables to flash after PCI configurationTimothy Pearson
2016-04-10nb/intel/sandybridge/raminit: always use mrccachePatrick Rudolph
2016-04-08Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"Timothy Pearson
2016-04-08nb/amd/mct_ddr3: Reenable sync flood after ECC initTimothy Pearson
2016-04-08nb/amd/mct_ddr3: Add MCE reporting logicTimothy Pearson
2016-04-08nb/amd/amdfam10: Only flag machine check exception if valid bit is setTimothy Pearson
2016-04-08nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform levelTimothy Pearson
2016-04-05nb/intel/sandybridge/raminit: die in toplevel functionPatrick Rudolph
2016-04-05nb/intel/sandybridge/raminit: prepare raminit for fallbackPatrick Rudolph
2016-04-01nb/amd/mct_ddr3: Fix revision mask for DR processorsTimothy Pearson
2016-03-31nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstageTimothy Pearson
2016-03-31nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEsTimothy Pearson
2016-03-31nb/amd/mct_ddr3: Disable MCE framework during DRAM trainingTimothy Pearson
2016-03-30nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installedTimothy Pearson
2016-03-30northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)Damien Zammit
2016-03-30nb/intel/sandybridge/raminit: move ram training into seperate functionPatrick Rudolph
2016-03-29nb/intel/sandybridge/raminit: move dimm_info into ramctr_timingPatrick Rudolph
2016-03-28nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()Timothy Pearson
2016-03-26nb/amd/amdmct: Select max_lanes based on ECC presence or absenceDamien Zammit
2016-03-24nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained valuesTimothy Pearson
2016-03-23nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_...Timothy Pearson
2016-03-21nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain setTimothy Pearson
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
2016-03-13nb/amd/mct_ddr3: Use correct initial UI setting during DRAM trainingTimothy Pearson
2016-03-13northbridge/intel/i3100: Unify UDELAY selectionStefan Reinauer
2016-03-13northbridge/intel/i82810: Unify UDELAY selectionStefan Reinauer
2016-03-12northbridge/intel/i82830: Unify UDELAY selectionStefan Reinauer
2016-03-12nb/amd/mct_ddr3: Consolidate duplicated codeTimothy Pearson
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
2016-03-11nortbridge/sandybridge/mrccache: parse the return code of flash->writeAlexander Couzens
2016-03-11nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15Timothy Pearson
2016-03-11nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetchTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Require minumum training quality for both read and writeTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latencyTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Properly initialize arrays and add bounds checksTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Restore previous DQS delay values on failed loopTimothy Pearson
2016-03-11northbridge/i945/gma: Re-enable NVRAM tft_brightnessAlexander Couzens
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
2016-03-09northbridge/intel/gm45: Use TSC for ramstage timer per defaultStefan Reinauer
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
2016-02-28northbridge/intel: add missing #include guardsIru Cai
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