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2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-22amd/agesa: Make BottomIo position configurableMike Banon
Some PCI peripherals, such as discrete VGA adapters, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. 0x80000000 has been successfully boot-tested on A88XM-E (fam15tn), G505S (fam15tn) and AM1I-A (fam16kb). Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-04-22nb/intel/haswell: Deprecate WDB params in pei_dataAngel Pons
The WDB (Write Data Buffer) is a data region in CAR, used as a scratchpad in the read and write training algorithms of memory initialization. Both SNB and IVB use this buffer, but HSW does not. Unlike earlier chipsets, Haswell contains much more in-hardware memory training machinery, known as REUT (Robust Electrical Unified Testing). Among other changes, the REUT hardware has a pattern storage buffer, which renders the need for a pattern storage buffer in CAR obsolete. Deprecate the WDB-related parameters in the pei_data structure for Haswell, as they are leftovers from the previous generation's MRC. Remove them from the mainboards, and explain why they are not required. Because the MRC ABI has to remain the same, the layout of pei_data must not be changed, so rename the WDB parameters instead of deleting them. Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf. Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-04-19nb/intel/sandybridge: Refactor get_mem_min_tckAngel Pons
It is not necessary to pass its value around various function calls. Move it closer to where it is actually used, so as to make it static. Also, use config_of_soc and flip the branches of the first conditional. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18asus/p2b*: Move serial init into mainboard bootblockKeith Hui
With this bootblock messages are transmitted over serial too. TEST=Serial messages transmitted normally on asus/p2b-ls. Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14nb/intel/sandybridge/raminit: Add ECC supportPatrick Rudolph
Add ECC support for native raminit on SandyBridge/IvyBridge. Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14nb/intel/sandybridge/raminit: Add ECC detection supportPatrick Rudolph
Add support for detection ECC capability and forced ECC mode. Print the ECC mode in verbose debugging mode. Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14nb/intel/i945: Add vboot supportArthur Heymans
Change-Id: I749be0044be04b044ff82e96aff8093f4b0d295e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-11nb/i945: Improve code formattingElyes HAOUAS
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-09nb/intel/i945: Use 'const' to set pci_devfn_t staticallyElyes HAOUAS
Change-Id: I879dd2fc61bc385486b506e2123f32629a67f518 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-07nb/amd/pi/00730F01/northbridge.c: refactor IVRS generationMichał Żygowski
Use defined structures to assemble IVRS and IVHD entries. Additionally assemble IVHD type 11h which supersedes IVHD type 10h. In order to utilize all IOMMU features firmware should also expose IVHD type 11h. The new type is already supported and parsed since Xen 1.13. IVHD type 10h should still be present for backwards compatibility. TEST=boot PC Engines apu2 and disassemble IVRS using newest IASL, boot Xen 1.13 or newer with debug enabled and see IVRS IVHD 11h parsed in xl dmesg Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9a2c24b67adfa8ebd718caeb5eec88687dcbcc9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02nb/intel/pineview: drop intel_gma_get_controller_info()Matt DeVillier
No longer used by southbridge, no longer needed since pineview doesn't utilize drivers_intel_gma_displays_ssdt_generate() Change-Id: Ia386f8fcd208e201fb8bc2a37cdbecd6f45a044b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39960 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02nb/intel/gm45: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Ideddfc3d327c4421faffb6583e347cd2b094e155 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/i945: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: I68848516fab2058d4aa96ac0342c883fd1df2d6d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/x4x: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Iacce01ab7d6c220779e84c2b695fbb597b493586 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/ironlake: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: I1b6d57c091441aa7431061b1f16135d54cc97b47 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/sandybridge: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: If34ebe0edc46674244c9d5afc7ed165c2ad685ba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02nb/intel/haswell: Simplify GMA SSDT generatorMatt DeVillier
Simplify generation of GMA SSDT, using updated naming convention. If acpi_fill_ssdt is being invoked, then we know the IGD device is present and enabled, so we can skip those checks. And the SSDT generator now checks that the gfx struct is populated, so we can skip that too. Change-Id: Icd9caf622dd4c46b13589ebb772138b25888752f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31drivers/intel/gma: fold gma.asl into default_brightness_levels.aslMatt DeVillier
Including gma.asl at the platform level (vs the board level) means that even desktop boards need to include the default brightness levels, which makes no sense. To begin to clean this up, include gma.asl in default_brightness_levels.asl (as well as the handful of board-specific brightness files) and remove it from the various platforms. A follow-on commit will remove default_brightness_levels.asl from all boards which lack an internal display. Change-Id: I8063deeef4ab6d6ab34ed9b0be5b1d541d6e9b6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39878 Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30nb/intel/i945: Make some cosmetic changesElyes HAOUAS
This will make i945GC and i945GM splitting easier. Change-Id: I3acc1f526056248f8fbb1778a3c381d369faf020 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29nb/intel/haswell: Implement proper backlight PWM configNico Huber
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code. We assume that the 183Hz value that was set before for Slippy variants was overridden by Linux with the 200Hz VBT value, like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane and also matches the VBT. Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-26nb/intel/sandybridge: Use macros for JEDEC commandsAngel Pons
Some commands, like ZQCS and ZQCL, use the same macro. This is because they differ in things outside of the IOSAV_SP_CMD_CTRL registers. Also, correct a comment that does not concur with the actual command in use. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: Id2ff4c85f9d9db7c892b764472423cbf2e6db422 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-26nb/intel/sandybridge: Fix IOSAV register descriptionAngel Pons
The four CS control signals are grouped into the same nibble. Change-Id: Iaf8d5216fdca6014be61ae2583fc963d69111571 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-26nb/intel/sandybridge: Correct TC_DTP handlingAngel Pons
It is only for Ivy Bridge, and needs to be set on certain circumstances. Change-Id: I4093adef44fae787c96fec4b4b8c7c867786d219 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-26nb/intel/sandybridge: Add and use TC_DTP definitionAngel Pons
This register is specific to Ivy Bridge. This changes the binary because the operations get reordered, but it is equivalent. Change-Id: Ibc9127e0fc268466c13f7c5ac8d942543713ca32 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-26nb/intel/sandybridge: Use IOSAV_BYTE_SERROR_C_ch macroAngel Pons
This changes the binary because the operations get reordered, but it is otherwise equivalent. Change-Id: I362187b2889e6f7a68bf752a23c1279cebf961f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-26nb/intel/sandybridge: Update commentAngel Pons
Expand a comment with additional information, and split it in two lines. Change-Id: I10389a1a575833c8ecc9a79a374c1816000f5667 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-26nb/intel/sandybridge: Rename raminit_ivy.cAngel Pons
It is no longer specific to Ivy Bridge. Change-Id: I3684e654a1b1aee308e30db739d41cf18e7ea6bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39790 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26nb/intel/sandybridge: Drop dead codeAngel Pons
Sandy Bridge now uses the same code as Ivy Bridge. Drop the old code. Change-Id: I4f6a71a4223194d83c0ee790d317ecdcafd664fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-26nb/intel/sandybridge: Unify the code pathsAngel Pons
The code for Sandy Bridge is a subset of the code for Ivy Bridge. Adapt the Ivy Bridge code so that it also supports Sandy Bridge, and use it. Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330. Change-Id: I7b78ec605aff976b9a5cdbb364a69df4b4947c6e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39737 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26nb/intel/sandybridge: Add print for PLL_REF100_CFGAngel Pons
This field can take eight different values, depending on the maximum supported speed for the memory when using the 100 MHz reference clock. Change-Id: I8f2f04f9444831319d4f7bf0d246d01030b6f864 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-26nb/intel/sandybridge: Rewrite get_FRQAngel Pons
The code is just clamping the frequency index to a valid range. Do it with a helper function. Also, add a CPUID check, as Sandy Bridge will eventually use this code. Change-Id: I4c7aa5f7615c6edb1ab62fb004abb126df9d284b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-25nb/intel/sandybridge: Cache FRQ indexAngel Pons
It does not change once a frequency has been set, so store it somewhere. Since this changes the saved data definition, update MRC_CACHE_VERSION. As SNB will eventually use the same code, only IVB is being refactored. Change-Id: I25b7c394abab173241fffdf57ac5c929daad8257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-25nb/intel/sandybridge: Rewrite table accessorsAngel Pons
There is no need to call get_FRQ a dozen times with the same parameters. As SNB will eventually use the same code, only IVB is being refactored. Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330. Change-Id: Idd7c119b2aa291e6396e12fb29effaf3ec73108a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-25amd/common/acpi: move thermal zone to common locationMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I048d1906bc474be4d5a4e44b9c7ae28f53b49d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25drivers/intel/gma/acpi: Add Kconfigs for backlight registersNico Huber
Instead of adding more versions of the `*pch.asl`, unify the existing ones and allow to override the register locations via Kconfig. The current defaults should work for Skylake and some newer platforms. TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2020-03-25acpi: correct the processor devices scopeMichał Żygowski
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25nb/intel/sandybridge: Factor out timing tablesAngel Pons
The timing tables for Sandy Bridge are a subset of Ivy Bridge's tables. Move the latter to a common place, and use it for both generations. Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, both work. Change-Id: Id14227febf4eebb8a2b4d2d4f37759d0f42648c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39735 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25nb/intel/sandybridge: Use SPDX headersAngel Pons
Note that pei_data.h uses the BSD 3-Clause license: https://opensource.org/licenses/BSD-3-Clause Change-Id: I904b343283239af4fdee583bcbea757f59a0cca7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-23nb/amd/pi/00730F01/state_machine.c: unhardcode IOAPIC2 addressMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I95964ac6b5939f66c40bd56939bdf532a72d75ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/39701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-23nb/amd/pi/00730F01: initialize GNB IOAPICMichał Żygowski
Northbridge IOAPIC was not being initialized which caused its APIC ID to be set to 0 (the same APIC ID as BSP). TEST=boot Debian Linux on PC Engines apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id06ad4c22a56eb3559e1d584fd0fcac1f95f13e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-23nb/intel/sandybridge: Use cached CPUIDAngel Pons
Now that we have it, we might as well pass it around. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Void MRC cache if CPUID differsAngel Pons
Native raminit asserts that the DIMMs haven't been replaced before reusing the saved training data. However, it does not check if the CPU is still the same, so it can end up happily reusing data from an Ivy Bridge CPU onto a Sandy Bridge CPU, which runs the raminit_ivy.c code path. This can make the CPU run in unsupported configurations, which may result in an unstable system, or a failure to boot. To prevent that, ensure that the stored CPUID matches the CPUID of the installed CPU. If they differ, print a message and do not use the saved data. As it does not pose a problem for a regular boot, but precludes resuming from S3, use different loglevels depending on the bootpath. Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, works well. Change-Id: Ib0691f1f849b567579f6afa845c9460e14f8fa27 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23nb/intel/sandybridge: Store CPUID in ctrl structAngel Pons
Instead of storing an int with a single bit of information taken from the CPUID, we might as well store the actual CPUID. And since we are changing the definition of the saved data, bump the version number. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: I6ac435fb83900a52890f823e7614055061299e23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39720 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 19:05:26 +0000