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Some coreboot project code with my work
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northbridge
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Commit message (
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Author
2021-02-01
nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>
Elyes HAOUAS
2021-02-01
nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>
Elyes HAOUAS
2021-02-01
nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h>
Elyes HAOUAS
2021-02-01
nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>
Elyes HAOUAS
2021-02-01
nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>
Elyes HAOUAS
2021-02-01
nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h>
Elyes HAOUAS
2021-02-01
nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BAR
Angel Pons
2021-02-01
nb/intel/haswell: Calculate TSEG limit from registers
Angel Pons
2021-02-01
nb/intel/haswell: Create RMRR for iGPU
Angel Pons
2021-01-30
nb/intel/i945: Define and use MMCONF_BUS_NUMBER
Angel Pons
2021-01-30
nb/intel/gm45: Define and use MMCONF_BUS_NUMBER
Angel Pons
2021-01-30
nb/intel/x4x: Define and use MMCONF_BUS_NUMBER
Angel Pons
2021-01-30
nb/intel/pineview: Define and use MMCONF_BUS_NUMBER
Angel Pons
2021-01-30
nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhere
Angel Pons
2021-01-30
nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBER
Angel Pons
2021-01-30
nb/intel/haswell: Define and use MMCONF_BUS_NUMBER
Angel Pons
2021-01-30
nb/intel/ironlake: Use RCBA macros
Angel Pons
2021-01-29
device/Kconfig: Declare MMCONF symbols' type once
Angel Pons
2021-01-27
nb/intel/haswell/haswell.h: Do not include `pch.h`
Angel Pons
2021-01-27
sb,soc/amd: Rename PMOD to PICM in ASL
Kyösti Mälkki
2021-01-25
nb/intel/ironlake: Drop constant parameter
Angel Pons
2021-01-25
nb/intel/sandybridge: Only run DMI recipe on Ivy Bridge
Angel Pons
2021-01-25
nb/intel/sandybridge: Correct late DMI init sequence
Angel Pons
2021-01-24
cpu/intel/haswell: Set C9/C10 vccmin
Angel Pons
2021-01-21
cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE
Elyes HAOUAS
2021-01-19
nb/intel/pineview/northbridge.c: Fix overlapping resources
Arthur Heymans
2021-01-19
nb/intel/pineview/northbridge.c: Improve readability
Arthur Heymans
2021-01-19
nb/intel/i945/northbridge.c: Reserve upper part of lower memory
Arthur Heymans
2021-01-19
nb/intel/i945/northbridge.c: Improve readability
Arthur Heymans
2021-01-19
nb/intel/ironlake/northbridge.c: Fix overlapping resources
Arthur Heymans
2021-01-19
nb/intel/ironlake/northbridge.c: Improve readability
Arthur Heymans
2021-01-19
nb/intel/ironlake/ironlake.asl: Remove sandy bridge copy pasta
Arthur Heymans
2021-01-19
nb/intel/ironlake: Remove chromeos copy pasta
Arthur Heymans
2021-01-19
nb/intel/ironlake: Print MCH dev/revision IDs and CAPID
Angel Pons
2021-01-18
nb/intel/gm45: Reserve MMIO and firmware memory below 1MiB
Nico Huber
2021-01-18
Revert "nb/intel/gm45/gm45.h: Remove duplicated include"
Patrick Georgi
2021-01-18
northbridge/intel/x4x/dq_dqs.c: Remove repeated word
Elyes HAOUAS
2021-01-18
northbridge/intel/gm45/bootblock.c: Remove repeated word
Elyes HAOUAS
2021-01-18
northbridge/intel/x4x/raminit_ddr23.c: Remove repeated word
Elyes HAOUAS
2021-01-18
northbridge/intel/sandybridge/bootblock.c: Remove repeated word
Elyes HAOUAS
2021-01-18
nb/intel/gm45/gm45.h: Remove duplicated include
Elyes HAOUAS
2021-01-18
lib/ramtest: Fix ram_check() declarations
Kyösti Mälkki
2021-01-15
nb/intel/sandybridge: Clarify command timing calculation
Angel Pons
2021-01-15
nb/intel/sandybridge: Fix handling of clock timing
Angel Pons
2021-01-15
nb/intel/sandybridge: Remove wrong and nonsense condition
Angel Pons
2021-01-15
nb/intel/x4x: Clean up raminit comments
Angel Pons
2021-01-15
nb/intel/x4x: Reset DQS probe on all channels
Angel Pons
2021-01-15
nb/intel/pineview: Extract HPET setup and delay function
Angel Pons
2021-01-10
nb/intel/gm45: Guard macro parameters
Angel Pons
2021-01-10
nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parameters
Angel Pons
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