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path: root/src/northbridge
AgeCommit message (Expand)Author
2011-03-28Add AMD C32 support.Zheng Bao
2011-03-08Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expect...Scott Duplichan
2011-03-01Mark non-returning function as noreturn to help some compiler versionsPatrick Georgi
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-27Add 300 MHz and 500 MHz HT frequency limitsXavi Drudis Ferran
2011-02-24Add compile-time defaults to some K8 CMOS options in case they're absent in CMOSJosef Kellermann
2011-02-21[i945] Add SPD adress mappingSven Schnelle
2011-02-14Errata #169 works on HT, not MCJosef Kellermann
2011-02-14This code provides cpu northbridge initialization for Family 14h cpus. It is ...Frank Vibrans
2011-02-10Implemented workaround for erratum 169, obsoleting erratum 131.Alexandru Gagniuc
2011-01-27SMM code on i945 platforms needs udelay()Peter Stuge
2011-01-20For Cx, each ChipSel need to be sent MR command.Zheng Bao
2011-01-19Add a GX2 Kconfig option to choose the framebuffer size.Nils Jacobs
2011-01-17The code is tested on my board with register DIMMs. More tests need to beZheng Bao
2011-01-06Fix some settings fo AMD MCT. It is based on BIOS test suite.Zheng Bao
2010-12-30Use die() to assure the processor can't wake up from an interrupt.Nils Jacobs
2010-12-29-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)Nils Jacobs
2010-12-29fix i810 boards with ram init debugging disabled.Stefan Reinauer
2010-12-27proper printk handling in src/northbridge/intel/i82810/raminit.cStefan Reinauer
2010-12-27__PRE_RAM__ is defined by the makefileStefan Reinauer
2010-12-27dump_spd_registers() is only defined when ram init debugging is on.Stefan Reinauer
2010-12-27Fix most CONFIG_DEBUG_RAM_SETUP issues. Stefan Reinauer
2010-12-26Move Geode GX2 UMA video memory size to KconfigNils Jacobs
2010-12-26Remove dead and unused Geode GX2 codeNils Jacobs
2010-12-26Replace Geode GX2 MSR addresses for GLCP on GLIU1 with namesNils Jacobs
2010-12-26Clean up Geode GX2 comments, whitespace and coding style. Trivial.Nils Jacobs
2010-12-23Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk().Keith Hui
2010-12-19The same mechanisms are used for normal and fallback images. Stefan Reinauer
2010-12-18Fix a few whitespace and coding style issues.Uwe Hermann
2010-12-18A couple of Poulsbo fixes:Patrick Georgi
2010-12-18Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 boardPatrick Georgi
2010-12-17drop one more version of doing serial uart output differently.Stefan Reinauer
2010-12-16fix according to coding guidelinesStefan Reinauer
2010-12-13Attached patch implements the memory speed reductions (and 2T/1T clock logic)...Rudolf Marek
2010-12-13Following patch adds support for suspend/resume functions. I had to change th...Rudolf Marek
2010-12-13Following patch adds support to bring out the memory out of self refresh when...Rudolf Marek
2010-12-13We hardcode highmemory size in every northbridge! This is bad, and especiall...Rudolf Marek
2010-12-11catch some illegal configurations (trivial)Stefan Reinauer