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2016-10-24nb/i945/Kconfig: select the correct VGA_BIOS_ID for 945GCArthur Heymans
Change-Id: I48ae27c5460020b9118e6ade1a3e610b542999c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17040 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19nb/i945/gma.c: use IS_ENABLED instead of #if, #endifArthur Heymans
Change-Id: Ib58126e1c9001ed679e161d6d06241fac762bdb3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17049 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPUArthur Heymans
The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect. The result is that 800MHz FSB CPUs now properly work with 667MHz RAM. Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas Elyes. Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17038 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19nb/i945/raminit: Add fix for 1067MHz FSB CPUsArthur Heymans
Previously the 945gc raminit only worked for 533MHz FSB CPUs. This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are taken from the vendor bios of Gigabyte ga-945gcm-s2l. The result is that 1067MHz FSB CPUs now boot without problems. 800MHz FSB cpus still don't get past romstage. Change-Id: I13a6b97d2e580512155edf66c48405a153121957 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17034 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19nb/gm45,x4x/gma.c remove writes to nonexisting FDI registersArthur Heymans
This removes writes to FDI related registers since there is no FDI link on these targets. This is likely a remainder from copying code from later targets. TESTED on Thinkpad x200 (gm45) Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16993 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-19nb/i945,gm45,x4x/gma.c: fix unsigned arithmeticsArthur Heymans
This issue was found by Coverity Scan, CID 1364118. Change-Id: Iba3c0f4f952729d9e0987d928b63ef8b8fe8841e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16992 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-19nb/gm45,x4x/gma.c: Compute p2 in VGA init instead of hardcoding itArthur Heymans
According to: "Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller PR" the p2 divisor needs to be 10 when the dotclock is below 225MHz and 5 when its above 225MHz. Change-Id: I363039b6fd92051c4be4fdc88788f27527645944 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16991 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-18northbridge/via/vx800: Convert 'for (;;)' to 'die'Elyes HAOUAS
Change-Id: I3f99190401d8df1415328da9c3b928194593901c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16989 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-15nb/i945/gma.c: correct VSYNC end offsetArthur Heymans
According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" the VSYNC end should start at bit 16. This is also how Linux (at least 4.4) sets this register, which can be seen with intel-gpu-tools. TESTED on Lenovo thinkpad X60 (it does not change anything). Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17015 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-12i945/gma.c: Only init LVDS if it is detectedArthur Heymans
Some devices have no LVDS output but if no VGA is connected or no EDID can be found, it will try to init LVDS. This patch detects the presence of an LVDS panel and makes sure that LVDS is not initialized when it is absent. Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16513 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11nb/gm45/gma.c: use linux code to compute LVDS dotclock divisorsArthur Heymans
This reuses linux code (at least 4.1) to compute the graphic clock divisors for LVDS displays on the gm45 northbridge. The divisors m1, m2, n, p1, p2 need to be such that "BASE_FREQUECY * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / (p1 * p2)" is as close as possible to the target_frequency. On g4x hardware the BASE_FREQUENCY is 96000kHz. This potentially increases LVDS display compatibility. Change-Id: I2323af5756431e89769f95059790f5a922af14b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16741 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-11nb/intel/*/graphic_init: use sizeof instead of hardcoding edid sizeArthur Heymans
Change-Id: I2b8c4ef75cca9f9d5251789cda4187a02076b69d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16964 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11i945/raminit.c: correctly write CLKCFG for 945GCArthur Heymans
MHCBAR(CLKCFG) was previously incorrectly written by the sdram_program_memory_frequency function which required falsely limiting the max dram frequency for 945GC. TESTED on Intel d945gclf (memclock 667 and fsb 533) and Gigabyte ga-945gcm-s2l (memclock 667 and fsb 1067) Change-Id: I520efd69fa09fc9fde87c5301fd81121fde6a700 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-10-11cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZENico Huber
An epic battle to fix Nehalem finally ended when we found an odd mask set in SMRR. This was caused by a wrong calculation of TSEG size. It was assumed that TSEG spans the whole space between TSEG base and GTT. This is wrong as TSEG base might have been aligned down. TEST: On X201, copied 1GiB from usb key to sd-card and verified. Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7 Found-by: Alexander Couzens, Nico Huber Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16939 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-10intel/i945: Use "IS_ENABLED" for fsbclk & memclkElyes HAOUAS
Change-Id: I3213a8664955239b10bcf1784ce1ba5e0d95688b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16958 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-10-10x4x/gma.c: Add VESA native resolution modeArthur Heymans
This patch implements native resolution, VESA mode, on the VGA output of x4x. It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ 60Hz) if this is no EDID could be found. This fallback mode only works in textmode since in VESA mode some payloads (grub2) rely on VBE info, which is being generated from an EDID. Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16498 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10northbridge/intel/nehalem: Remove commented codeElyes HAOUAS
Change-Id: I2d40049a27f725f14acbc16438f0e6ea7cdd7329 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16879 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10northbridge/intel/i440bx: Remove commented codeElyes HAOUAS
Change-Id: I0dd8c32f1b9165fe8c449cee1c21a155a725c04f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16878 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09src/northbridge/via: Remove commented codeElyes HAOUAS
Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16898 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family15*: Remove commented codeElyes HAOUAS
Change-Id: If372655700c18340d51368a39392560f664f4a45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family14: Remove commented codeElyes HAOUAS
Change-Id: I04fe6b7a8798d0f3cb54130283ce5a50eb9ac5b4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16895 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdk8: Remove commented codeElyes HAOUAS
Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16893 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/lx: Remove commented codeElyes HAOUAS
Change-Id: I37c1674ee380936aba797e24897593fcca3b0269 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16891 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/pi/00730F01: Remove commented codeElyes HAOUAS
Change-Id: I930c761b9a2422590af3a0a5008b4ff2abe3fd96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16890 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdmct/mct_ddr3: Remove commented codeElyes HAOUAS
Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16889 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family16kb: Remove commented codeElyes HAOUAS
Change-Id: Ic22f8a00e6009e104df8c4374067369ebbf90ee2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16888 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family15rl: Remove commented codeElyes HAOUAS
Change-Id: I5f45a4cd5661140f57aa37e86cc8a34622da3de5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16887 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family10: Remove commented codeElyes HAOUAS
Change-Id: I7966f996a4291cc6b97b53aba59b43358de94e45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16886 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdfam10: Remove commented codeElyes HAOUAS
Change-Id: I63fee62253cb0488a041c9985a646102261b8c5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16880 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/northbridge: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04nb/gm45: allow use of 352M preallocated ram for igdArthur Heymans
The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family" mention the possibility of having 352M ram preallocated for the integrated graphic device. This only worked fine if the amount of ram in the system was 3GB or less. When 4G or more is installed, memory is remapped to create a 1GB large pci mmio hole which is not enough and creates conflicts when 352M vram is used. This patch increases the pci mmio hole size on Lenovo x200 to allow 352M vram to work. TEST: build and flash on target with 4GB ram or more, use nvramtool to set gfx_uma_size to 352M and reboot. Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16831 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/northbridge: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Iea0352f85f4d5f47fc906edbe625e7bbf3f03afd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16863 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-01northbridge/via/cn700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/via/cn700. Change-Id: Ib7761697daad3c459f3568e5158f925199bcd919 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16689 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30mb/intel/d945gclf: Allow use of native graphic initArthur Heymans
Add PCI device id to native graphic init and add the Native graphic init option in Kconfig. Change-Id: I136122daef70547830bcc87f568406be7162461f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16512 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30i945/gma.c: add native VGA initArthur Heymans
This reuses the Intel Pineview native graphic initialization to have output on the VGA connector of i945 devices. The behavior is the same as with the vendor VBIOS BLOB. It uses the external VGA display if it is connected. Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16511 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30i945/gma.c: use linux code to calculate divisorsArthur Heymans
The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. The divisors must be such "refclk * (5 * (m1 + 2) + (m2 + 2))/ (n + 2) / (p1 * p2)" is as close as possible to the target frequency (which is defined by the resolution and refresh rate). This patch also fixes the reference frequency. This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c to correctly compute divisors. The result is that some previously not working displays, like many displays found on the Lenovo T60 might work now. Some examples of T60 displays that were known to not work (in payload): Samsung LTN141XA-L01 (14.1" 1024x768) LG-Philips LP150X09 (15.1" 1024x768) IDtech N150U3-L01 (15.1" 1600x1200) IDtech IAQX10N (15.1" 2048x1536) Samsung LTN154X3-L0A (15.4" 1280x800) LG-Philips LP150E06-A5K4 (15.1" 1400x1050) Tested on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16504 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-27northbridge/sandybridge/raminit_mrc.c: fix missing includeMatt DeVillier
Compilation (w/o native raminit) fails due to missing include Change-Id: Ic79a77006257b32e0181c88c4e24d7c1f5c5f7ce Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/16735 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-27i945/gma.c: Generate fake VBTArthur Heymans
This generates a fake VBT for the Intel i945 graphic device. i945 supports both the mobile chipset 945gm (calistoga) and the desktop chipset 945gc (lakeport), which is why a VBT with a different id string needs to be created for each target. The VBT id string is obtained from the vbios blob in the following way: "strings vbios.bin | grep VBT". Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16530 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-27nb/intel/*/gma.c: remove spaces at the fake vbt generationArthur Heymans
Padding the VBT id string is now done automatically. Change-Id: I8f9baf7b1585026bc29b82d07e451aa11e284ffb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16740 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-21northbridge/amdk8: Improve code formattingElyes HAOUAS
Change-Id: I1c2786dfb166904ff8b19a663c5e2e8156b7aedf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16644 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-21northbridge/amd/amdmct: Improve code formattingElyes HAOUAS
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21northbridge/amd: Improve code formattingElyes HAOUAS
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/amd/amdfam10: Improve code formattingElyes HAOUAS
Change-Id: I86a252598666af635281eaa467020acb53d71c77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/via: Add space around operatorsElyes HAOUAS
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16623 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-20northbridge/intel/e7505/debug.c: Improve code formattingElyes HAOUAS
Change-Id: I63f58d95fa01b1f73f3620a5d13f21ef62e2404c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i3100: Add space around operatorsElyes HAOUAS
Change-Id: I5ff894f23dc2a2c59bc5e5d1de4287a6b9c9922c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i945: Add space around operatorsElyes HAOUAS
Change-Id: I24505af163544a03e3eab72c24f25fcdc4b1b16c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16624 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/amd/agesa: Improve code formattingElyes HAOUAS
Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7505: Improve code formattingElyes HAOUAS
Change-Id: I964512c0e913f7443f3dea859b01358645cfd8a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16632 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i82830: Add space around operatorsElyes HAOUAS
Change-Id: Ic4e287209cc45fae574e7af9d45b8a0e648ef686 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 04:57:29 +0000