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AgeCommit message (Expand)Author
2012-07-20Intel SCH northbridge: fix resource indexKyösti Mälkki
2012-07-16Drop invalid device ops on Agesa northbridgeKyösti Mälkki
2012-07-16AMD: Fix GFXUMA with 4GB or more RAMKyösti Mälkki
2012-07-16Move setup_uma_memory() to K8 northbridgeKyösti Mälkki
2012-07-16Move setup_uma_memory() to AMDFAM10 northbridgeKyösti Mälkki
2012-07-16Move setup_uma_memory() to Agesa Family14 northbridgeKyösti Mälkki
2012-07-16Move setup_uma_memory() to Agesa Family12 northbridgeKyösti Mälkki
2012-07-16Move setup_uma_memory() to Agesa Family15 northbridgeKyösti Mälkki
2012-07-16Define global uma_memory variablesKyösti Mälkki
2012-07-16Add global uma_resource()Kyösti Mälkki
2012-07-16i5000: Fix resource allocationSven Schnelle
2012-07-09i5000: reset system if raminit failsSven Schnelle
2012-07-06i5000: Add PCI ids for all i5000 flavoursSven Schnelle
2012-07-06i945: Reset IGD on bootPatrick Georgi
2012-07-03AGESA F15 wrapper for Trinityzbao
2012-06-21Don't use 64-bit constant 0x100000000 in linker scriptsNico Huber
2012-06-20i5000: fix another typoSven Schnelle
2012-06-20i5000: fix typosSven Schnelle
2012-06-18i5000: enforce hard resetSven Schnelle
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
2012-05-11Hook up MRC cache updateStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-05-08Some more #if cleanupPatrick Georgi
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
2012-05-02Make Intel i5000 specific options only appear on i5000 systemsStefan Reinauer
2012-05-02Strip quotes from Sandybridge MRC blobStefan Reinauer
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
2012-05-01Update Ivybridge GT power meter tablesDuncan Laurie
2012-05-01Update ivybridge graphics initializationDuncan Laurie
2012-05-01Only send ME Dram Init Done message on SandybridgeDuncan Laurie
2012-05-01Modify DMI init for IvyBridgeVincent Palatin
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
2012-04-30Sandybridge: Temporarily disable MRC cache finding codeStefan Reinauer
2012-04-30Add default map_oprom_vendev() for AMD Family 14h processors.Martin Roth
2012-04-28Reverse Vendor ID & Device ID for map_oprom_vendev()Martin Roth
2012-04-27SMM: Add udelay on Sandybridge systemsStefan Reinauer
2012-04-21Intel e7505: build as separate object fileKyösti Mälkki
2012-04-21Intel e7505: enable ECC scrubbingKyösti Mälkki
2012-04-20Refactor some alignment handlingPatrick Georgi
2012-04-19Intel e7505: refactor onlyKyösti Mälkki
2012-04-17Intel e7505: handlers for undocumented registersKyösti Mälkki
2012-04-16S3 code in coreboot public folder.zbao
2012-04-12Unify IO APIC address specificationPatrick Georgi
2012-04-11Intel e7505: cleanupsKyösti Mälkki
2012-04-11Intel e7505: renames onlyKyösti Mälkki
2012-04-05amdfam10: add phenom II as known cpuBernhard Urban
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
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