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path: root/src/northbridge
AgeCommit message (Expand)Author
2018-05-14nb/intel/i945/raminit.c: Remove not necessary braces {}Elyes HAOUAS
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
2018-05-14agesa/family16kb/northbridge: report acpi namespaceKevin Cody-Little
2018-05-11nb/intel/i945/bootblock.c: Correct commentElyes HAOUAS
2018-05-11nb/intel/i440bx: Get rid of device_tElyes HAOUAS
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
2018-05-04amd/mct/ddr3: Correctly configure CsMux67Patrick Georgi
2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
2018-05-01nb/intel/x4x: Fix programming CxDRBArthur Heymans
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
2018-05-01Fix freeze during chipset lockdown on NehalemMatthias Gazzari
2018-04-30nb/intel/fsp_rangeley: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/i440: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/pineview: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/nehalem: Get rid of device_tElyes HAOUAS
2018-04-30nb/x4x: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/i945: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/gm45: Get rid of device_tElyes HAOUAS
2018-04-28nb/intel/x4x: Fix computing page_sizeArthur Heymans
2018-04-28nb/intel/i945/gma: Skip native VGA init for ACPI S3 resumePaul Menzel
2018-04-28nb/intel/i945/gma: Factor out code to new `gma_ngi()`Paul Menzel
2018-04-25vx900: Drop some unused definesLubomir Rintel
2018-04-24compiler.h: add __weak macroAaron Durbin
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
2018-04-17nb/intel/x4x/rcven.c: Change the verbosity of some messagesArthur Heymans
2018-04-17nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans
2018-04-17nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans
2018-04-17nb/intel/x4x: Refactor setting default dll settingsArthur Heymans
2018-04-17nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans
2018-04-16nb/intel/i945/gma: Log native graphics init in level INFOPaul Menzel
2018-04-16nb/intel/i945/gma: Fix aligment of equal signPaul Menzel
2018-04-16nb/intel/sandybridge: support more XMP timingsDan Elkouby
2018-04-13nb/intel/sandybridge/peg: Add PEG driver stubPatrick Rudolph
2018-04-11Revert "model_206ax: Use parallel MP init"Arthur Heymans
2018-04-11model_206ax: Use parallel MP initArthur Heymans
2018-04-10cpu/intel/sandybridge: Put stage cache into TSEGArthur Heymans
2018-04-09intel/nehalem post-car: Use postcar_frame for MTRR setupKyösti Mälkki
2018-04-04nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbersJonathan Neuschäfer
2018-03-28nb/intel/gm45: Allocate a 8M TSEG regionArthur Heymans
2018-03-08nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APICMatt DeVillier
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