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path: root/src/northbridge
AgeCommit message (Expand)Author
2017-01-22nb/x4x/raminit: Fix programming dram timingsArthur Heymans
2017-01-20nb/gm45/gma.c: Fix reported Pixel clockArthur Heymans
2017-01-19nb/amd/ddr3: Make the maximum CDD a signed valueTimothy Pearson
2017-01-14amd/mct: Add default values to highest_rank_count for DDR2Timothy Pearson
2017-01-12amd/mct/ddr2: Remove orphaned Tab_TrefT_k variableTimothy Pearson
2017-01-11amd/mct/ddr3: Fix unintended sign extension warningTimothy Pearson
2017-01-11amd/mct/ddr3: Avoid using uninitialized register address in ECC setupTimothy Pearson
2017-01-11nb/i945/raminit.c: Use Makefile.inc instead of '#include rcven.c'Arthur Heymans
2017-01-11amd/mct/ddr3: Free malloced resources in failure branchesTimothy Pearson
2017-01-11amd/mct/ddr3: Rework memory speed to clock value conversion logicTimothy Pearson
2017-01-11amd/mct/ddr3: Correctly program maximum read latencyTimothy Pearson
2017-01-10amd/mct/ddr3: Allow critical delay delta to go negativeTimothy Pearson
2017-01-10amd/mct/ddr3: Correctly configure CsMux45Timothy Pearson
2017-01-10amd/mct/ddr3: Wait for northbridge P-state transitionsTimothy Pearson
2017-01-10nb/intel/945gc: Hardcode the integrated graphic frequenciesArthur Heymans
2017-01-10amd/mct/ddr3: Fix incorrect DQ mask calculationTimothy Pearson
2017-01-10amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStrucTimothy Pearson
2017-01-09amd/pi: Make BottomIo position configurableRicardo Ribalda Delgado
2017-01-06nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans
2017-01-06sb/ich7: Use common/gpio.h to set up GPIOsArthur Heymans
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
2016-12-21nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual ChannelElyes HAOUAS
2016-12-20nb/intel/haswell: Hook up libgfxinitArthur Heymans
2016-12-18intel/fsp_rangeley: Fix use of __SIMPLE_DEVICE__Kyösti Mälkki
2016-12-18intel cache-as-ram: Move DCACHE_RAM_BASEKyösti Mälkki
2016-12-17nb/x4x: Add other Eaglelake IGD PCI DID to listArthur Heymans
2016-12-16nb/intel/sandybridge/raminit: Separate Sandybridge and IvybridgePatrick Rudolph
2016-12-13nb/intel/gm45: Use lapic udelay in SMMMartin Roth
2016-12-11nb/intel/i945: Make pci_mmio_size a devicetree parameterArthur Heymans
2016-12-11ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP defaultKyösti Mälkki
2016-12-11intel/nehalem: Use romstage_handoff for S3Kyösti Mälkki
2016-12-11intel i945 gm45 x4x: Switch to RELOCATABLE_RAMSTAGEKyösti Mälkki
2016-12-11intel/i945: Use romstage_handoff for S3Kyösti Mälkki
2016-12-11intel/gm45: Use romstage_handoff for S3Kyösti Mälkki
2016-12-11intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki
2016-12-11intel i945 gm45 x4x: Apply cbmem_top() alignmentKyösti Mälkki
2016-12-09intel/sandybridge: Use postcar_frame for MTRR setupKyösti Mälkki
2016-12-08buildsystem: Drop explicit (k)config.h includesKyösti Mälkki
2016-12-08nb/intel/sandybridge: Lock PAVPCDennis Wassenberg
2016-12-07AMD fam10 binaryPI: Remove invalid PCI ops on CPU domainKyösti Mälkki
2016-12-07MMCONF_SUPPORT: Drop redundant loggingKyösti Mälkki
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
2016-12-06PCI ops: Remove conflicting duplicate declarationsKyösti Mälkki
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
2016-12-06AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already setKyösti Mälkki
2016-12-06intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
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