summaryrefslogtreecommitdiff
path: root/src/northbridge
AgeCommit message (Expand)Author
2015-11-06amd/00730F01: Fix MMCONF resourceKyösti Mälkki
2015-11-06AMD bettong: Fix the interrupt routing.zbao
2015-11-05nb/intel/sandybridge: Limit GFX workaround to Sandy BridgeNico Huber
2015-11-05src/amd: Increase maximum blootblock execution countTimothy Pearson
2015-11-04nb/intel/sandybridge: Add ACPI DMAR tableNico Huber
2015-11-04nb/intel/sandybridge: Enable basic IOMMU supportNico Huber
2015-11-04ACPI: Make DMAR flags settableNico Huber
2015-11-03via/cx700: remove unused #definePatrick Georgi
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
2015-11-02cpu/amd: Move model_10xxx to family_10h-family_15hTimothy Pearson
2015-11-02northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend overrunning the stack size limitTimothy Pearson
2015-11-02northbridge/amd/amdfam10: Set DIMM voltage based on SPD dataTimothy Pearson
2015-10-31northbridge/amd/amdfam10: Correct S3_DATA_POS type from int to hexTimothy Pearson
2015-10-31northbridge/amd/amdfam10: Update RAM speed table with DDR3 valuesTimothy Pearson
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-30Drop northbridge/i440lxStefan Reinauer
2015-10-30AMD mainboards: Fix 64bit BiosCallOuts.cStefan Reinauer
2015-10-30cpu/amd: Fix cbtypes.h to match UINTN conventionStefan Reinauer
2015-10-30RD890: 64bit fixesStefan Reinauer
2015-10-30northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) supportTimothy Pearson
2015-10-30northbridge/amd/amdfam10: Add Suspend to RAM (S3) Flash data storage areaTimothy Pearson
2015-10-30Port AGESA based northbridge code to 64bitStefan Reinauer
2015-10-29nb/intel/sandybridge/gma: add disable functionPatrick Rudolph
2015-10-29northbridge/amd/amdk8: Improve DIMM detection debuggingTimothy Pearson
2015-10-27northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendationsTimothy Pearson
2015-10-26northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalizationTimothy Pearson
2015-10-25AMD Family 0Fh: ensure CONFIG_CBB and CONFIG_CDB have sane valuesJonathan A. Kollasch
2015-10-25northbridge/amd/amdfam10: Enable advanced PCIe setup optionsTimothy Pearson
2015-10-24cpu/amd: Add initial support for AMD Socket G34 processorsTimothy Pearson
2015-10-23Intel: Move MCRS ResourceTemplate outside of _CRS methodMartin Roth
2015-10-23northbridge/amd/amdmct: Fix Family 15h detectionTimothy Pearson
2015-10-23northbridge/amd/amdmct/mct_ddr3: Fix curly brace style violationsTimothy Pearson
2015-10-23northbridge/amd/amdfam10: Fix typo in commentTimothy Pearson
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
2015-10-12gma: Consolidate Intel IGD ACPI code some moreNico Huber
2015-10-11Kill lvds_num_lanesVladimir Serbinenko
2015-10-11Derive lvds_dual_channel from EDID timings.Vladimir Serbinenko
2015-10-09nb/intel/sandybridge/raminit: Add edge write discovery checkPatrick Rudolph
2015-10-09northbridge/intel/sandybridge: Do not disable PEG by defaultPatrick Rudolph
2015-10-09northbridge/intel/sandybridge: Enable PEG clock-gating on demandPatrick Rudolph
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
2015-10-04northbridge/intel/nehalem: Fix native VGA initNicolas Reinecke
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-10-01northbridge/intel/gm45: Fix native VGA initAudrey Pearson
2015-09-30amd/family14: Add k10temp thermal zone.Tobias Diedrich
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 04:55:24 +0000