Age | Commit message (Expand) | Author |
2018-07-20 | AGESA binaryPI: Fix and optimize for MAX_NODES_NUM | Kyösti Mälkki |
2018-07-12 | nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs | Elyes HAOUAS |
2018-07-09 | src/northbridge: Use "foo *bar" instead of "foo* bar" | Elyes HAOUAS |
2018-07-02 | src/nb: Fix non-local header treated as local | Elyes HAOUAS |
2018-06-30 | arch/x86/acpi: Add DMAR RMRR helper functions | Matt DeVillier |
2018-06-29 | sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables | Arthur Heymans |
2018-06-29 | sb/intel/i82801ix: Use the common ACPI pirq generator | Arthur Heymans |
2018-06-23 | nb/intel/i945: Remove dead code | Elyes HAOUAS |
2018-06-21 | Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" | Arthur Heymans |
2018-06-20 | nb/intel/e7505: Leave ROM as un-cacheable in postcar | Kyösti Mälkki |
2018-06-17 | nb/intel/i440bx: Switch to POSTCAR_STAGE | Kyösti Mälkki |
2018-06-17 | nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGE | Kyösti Mälkki |
2018-06-17 | cpu/intel/slot_1: Switch to different CAR setup | Kyösti Mälkki |
2018-06-17 | nb/intel/nehalem: Fix DEVEN defines | Patrick Rudolph |
2018-06-17 | nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset | Arthur Heymans |
2018-06-14 | cpu/intel/haswell: Use the common intel romstage_main function | Arthur Heymans |
2018-06-14 | nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce | Elyes HAOUAS |
2018-06-14 | nb/intel/x4x: Deprecate native graphic init | Arthur Heymans |
2018-06-14 | nb/intel/x4x: Fix a few things in set_enhanced_mode | Arthur Heymans |
2018-06-14 | nb/intel/x4x: Work around a quirk | Arthur Heymans |
2018-06-14 | nb/intel/x4x: Add the option for stacked channel map settings | Arthur Heymans |
2018-06-14 | src: Get rid of unneeded whitespace | Elyes HAOUAS |
2018-06-14 | src: Get rid of device_t | Elyes HAOUAS |
2018-06-14 | src: Use of device_t is deprecated | Elyes HAOUAS |
2018-06-14 | AGESA binaryPI: Drop RAMBASE and RAMTOP | Kyösti Mälkki |
2018-06-11 | {src,util}: Use NULL instead of 0 for pointer | Elyes HAOUAS |
2018-06-08 | libgfxinit: Enable G45 support (for GM45/X4X) | Nico Huber |
2018-06-07 | nb/intel/pineview: Enable and allocate 8M for TSEG | Arthur Heymans |
2018-06-07 | nb/intel/i945: Enable and allocate 8M for TSEG | Arthur Heymans |
2018-06-07 | nb/intel/i945: Add a common function to compute TSEG size | Arthur Heymans |
2018-06-06 | intel/e7505: Remove ROMCC workaround | Kyösti Mälkki |
2018-06-06 | arch/x86: Make RELOCATABLE_RAMSTAGE the default | Kyösti Mälkki |
2018-06-06 | arch/x86: Flag platforms without RELOCATABLE_RAMSTAGE | Kyösti Mälkki |
2018-06-05 | northbridge/amd/lx: Fix function setShadowRCONF | Iru Cai |
2018-06-05 | amd/geode_lx: Fix .c includes | Kyösti Mälkki |
2018-06-05 | cpu/intel/haswell: Switch to POSTCAR_STAGE | Arthur Heymans |
2018-06-05 | cpu/intel/model_2065x: Switch to POSTCAR_STAGE | Arthur Heymans |
2018-06-05 | cpu/intel/model_206ax: Switch to POSTCAR_STAGE | Arthur Heymans |
2018-06-05 | nb/intel/gm45: Switch to POSTCAR_STAGE | Arthur Heymans |
2018-06-05 | nb/intel/x4x: Switch to POSTCAR_STAGE | Arthur Heymans |
2018-06-05 | nb/intel/pineview: Switch to POSTCAR_STAGE | Arthur Heymans |
2018-06-05 | nb/intel/i945: Switch to POSTCAR_STAGE | Arthur Heymans |
2018-06-04 | security/tpm: Unify the coreboot TPM software stack | Philipp Deppenwiese |
2018-06-04 | intel/i440bx: Drop tests for LATE_CBMEM_INIT | Kyösti Mälkki |
2018-06-04 | src: Use "foo *bar" instead of "foo* bar" | Elyes HAOUAS |
2018-06-04 | nb/intel: Use postcar_frame_add_romcache() | Nico Huber |
2018-06-04 | nb/via/vx900: Get rid of device_t | Elyes HAOUAS |
2018-06-04 | northbridge/intel: Remove unneeded includes | Elyes HAOUAS |
2018-06-02 | intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGE | Kyösti Mälkki |
2018-06-02 | intel/e7505: Move to RELOCATABLE_RAMSTAGE | Kyösti Mälkki |