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2004-01-14small fixesStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-13*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-08- Set all of the fields in config_busses before we use it not afterwards.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-08missing file.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-06- Fix amdk8_scan_root_bus and amdk8_scan_chains so multiple HT chainsEric Biederman
can be scanned in any order git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-02from Yh LuRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-27fix AMD Solo targetStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-15*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-15added sizeram and init routinesGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-15updated namesGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-15done in C nowGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-10automatically detect southbridge link. this should allow to get rid of mostStefan Reinauer
of the special resource maps spread over the opteron ports and make the code more generic git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-09changes for v2Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-05fixes for epia, attempts to fix arimaRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-04add hook for spdrom iohub selectionStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-23fixes from SONERonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-22fixes for EPIA.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-14- Minor bugfixesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-11 - O2, enums, and switch statements work in romccEric Biederman
- Support for compiling romcc on non x86 platforms - new romc options -msse and -mmmx for specifying extra registers to use - Bug fixes to device the device disable/enable framework and an amd8111 implementation - Move the link specification to the chip specification instead of the path - Allow specifying devices with internal bridges. - Initial via epia support - Opteron errata fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-03- Modify the code to C style indenting.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-02Some timing in here, but we don't set; it breaks.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-02ram size now set from SPD.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-02First SPD code in and working!Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-02success. It boots as a bproc slave now.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-30The epia now works.Ronald G. Minnich
Now to fix the ram ... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-27ok that's it. I think this might work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-27a few tweaks etc.Ronald G. Minnich
Still probably wrong. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26it's getting through the 8601 but the values are still not right.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26something is wrong here but not sure what.Ronald G. Minnich
But nothing is getting set into the north bridge. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26just to get us back where we were.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26via epia; also yh lu tyan.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-25first cut at 8601 supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-23make coherent ht setup capable of non-standard link configurationsStefan Reinauer
(i.e. with CPU1 not connected to ACROSS link of CPU0) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-04- Remove dead argument to hypertransport_scan_chainEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-03cosmeticsStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02- 1.1.4Eric Biederman
Major restructuring of hypertransport handling. Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically Updates to hard_reset handling when resetting because of the need to change hypertransport link speeds and widths. (a) No longer assume the boot is good just because we get to a hard reset point. (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the boot counter. Updates to arima/hdama mptable so it tracks the new bus numbers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01- Updates to config.g so that it works more reliably and has initial supportEric Biederman
for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc - Updates to config.g so that it works more reliably and has initial support for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc killed src/sdram/generic_dump_spd.inc killed src/sdram/generic_dump_spd.inc - Updated the arima/hdama to build with the new configuration system - Updated config.g to list all of the variables with make echo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-28more motherboard specific cleanupsStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-28cleaning out motherboard specific changes from the generic directories.Stefan Reinauer
Moving tyan resource map to tyan directory. Making IOMMU for hammer choosable via ENABLE_IOMMU git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04patches from Yh Lu. Tested and working on HDAMARonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-01- Update raminit.c so it works properly for multiple cpusEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-30updates from YhLu, plus fixes for PPC/K8 issues.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-25YhLu's changes to resolve several memory and other problems.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21- First pass at s2880 support.Eric Biederman
- SMP cleanups (remove SMP only use CONFIG_SMP) - Minor tweaks to romcc to keep it from taking forever compiling - failover fixes - Get a good implementation of k8_cpufixup and sizeram for the opteron git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21* update quartet target to latest SMP changes.Stefan Reinauer
* remove dead code from coherent_ht.c * add ldtstop code for link speed changes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-19- Major cleanup of the bootpathEric Biederman
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17moved generate_row from coherent_ht.c to board specific auto.c filesStefan Reinauer
due to different routing defaults of different boards. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- Update Config so we now have the proper number of cpusEric Biederman
- Remove some debugging code from auto.c - Update coeherent_ht.c so we get the proper broadcast routes. - Fix the dram probing code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- pci_device.c fixes for generic pci bridges to zero the unused portion of ↵Eric Biederman
bridge resources - coherent_ht.c remove dead idle loop. - raminit.c Enable a 64MB mmio window just below 4GB git-svn-id: svn://svn.coreboot.org/coreboot/trunk@967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16fix some glitches in cht code: always enable routing on node7, plus do ↵Stefan Reinauer
masking right when setting cpucnt/nodecnt git-svn-id: svn://svn.coreboot.org/coreboot/trunk@966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1