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2016-04-08nb/amd/mct_ddr3: Reenable sync flood after ECC initTimothy Pearson
The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 and related changes have made it possible to move the sync flood enable statements back into romstage. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14270 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08nb/amd/mct_ddr3: Add MCE reporting logicTimothy Pearson
When a fatal error and subsequent sync flood / reset occurs, the MCA status registers may contain valuable information on the cause of the fatal error. Add functions to report MCEs and reset the MCA status registers early in the boot process. Change-Id: Icde1051ac22f93688de1330f5e2c9ce28b14b59a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14265 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08nb/amd/amdfam10: Only flag machine check exception if valid bit is setTimothy Pearson
Change-Id: I42d901ae9445943a863fb3ba9bda5a915f255e02 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14264 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform levelTimothy Pearson
Certain AMD platforms, such as those using the SP5100 southbridge, contain a very poorly documented bug related to LPC ROM access, which is triggered by repeated (hundreds or more) rapid calls to get_option(). This bug manifests as a complete system deadlock in ramstage device configuration, requiring standby power to be removed from the system to release the deadlock. Cache the platform ECC status to avoid repeated calls to get_option() in the lane count detection logic. Change-Id: I8b48c523218ccc8c113319957d6eca2d15e1070f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14273 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-05nb/intel/sandybridge/raminit: die in toplevel functionPatrick Rudolph
In error case die in top level function. No functionality is changed. Change-Id: Ie15b01184d40bdbce20d49dcab2f9fb607068c7a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14171 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-05nb/intel/sandybridge/raminit: prepare raminit for fallbackPatrick Rudolph
Return errors to top level ram init function. Required by the folowing series to implement a fallback. No functionality is changed. On error case the system still halts in every test. Change-Id: I6278c4a1d7b4a96be8988a60671fc3d72cd6cb3d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-01nb/amd/mct_ddr3: Fix revision mask for DR processorsTimothy Pearson
The revision mask for all DR-* series processors was incorrectly set to only include the DR-B revision mask. Include all DR-* series prcessors in the DR_ALL revision mask. Change-Id: Iceda96aa6267b24abcbf78d39f4848d2be8053b8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Found-by: Coverity, CID 1229627 (#1 of 1): Logically dead code (DEADCODE) Reviewed-on: https://review.coreboot.org/14216 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-03-31nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstageTimothy Pearson
Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Also clear the DRAM ECC sync flood bits during DRAM training and initial ramstage execution. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14192 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-31nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEsTimothy Pearson
During power on from cold (S5) state, numerous MCEs are generated before DRAM training starts, e.g. during HT link training. Clear these MCEs before DRAM training start, and report any MCEs generated during DRAM training. Change-Id: I7d047571242e5bd041e4aac22c1ec1d7d26ef0e6 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14191 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-31nb/amd/mct_ddr3: Disable MCE framework during DRAM trainingTimothy Pearson
On Family 15h processors, with certain RDIMMs, MCEs are generated as a normal part of DCT startup / DRAM training. Disable sync flood on parity or UC data error until ECC has been enabled. Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14186 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-30nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installedTimothy Pearson
This resolves a long-standing issue with RDIMM control word configuration failure, likely due to random parity failure. Change-Id: If8b8dc5b8b99f4c2fe29b3a133b064631e4693be Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14184 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-30northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)Damien Zammit
Change-Id: I96d695ed10176276116fcf3a2b77605fb3f2d5db Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13710 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-30nb/intel/sandybridge/raminit: move ram training into seperate functionPatrick Rudolph
In order to add a fallback mechanism, move the ram training code into a new function. This function will be called multiple times and must return error or success to the calling function. Change-Id: I5ee1b3a528290d8252d236b9152b81291736958a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14169 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-29nb/intel/sandybridge/raminit: move dimm_info into ramctr_timingPatrick Rudolph
It's required to store the dimm_info in ramctr_timing as only ramctr_timing is written to mrc cache. Allows to fill SMBIOS type 17 if mrc cache is used. Change-Id: I7634b05069df307d471938d9854997a018de81b3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14168 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-28nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()Timothy Pearson
Replace open coded memset() functions with calls to the library function. The new code also explicitly backs up and restores the data structures that are preserved across calls to mct_ResetDataStruct_D(), and no longer relies on structure member order to function correctly. Change-Id: I6dd6377deda0087cd1b65f7555588978657d6516 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-26nb/amd/amdmct: Select max_lanes based on ECC presence or absenceDamien Zammit
Change-Id: Ic5482dc13ab7b53ec4df408bbe32d20888ae2e12 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13725 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-24nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained valuesTimothy Pearson
During maximum read latency training on Family 15h processors, the maximum read latency was incorrectly set from the NBP1 value instead of the correct NBP0 value. Modify maximimum read latency training to explicitly operate on the NBP0 value, and store the previously calculated NBP1 value for reference by other portions of the training algorithm. Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14150 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-03-23nb/amd/mct_ddr3: Remove spurious Addl_Index variable in ↵Timothy Pearson
dqsTrainMaxRdLatency_SW_Fam15() Change-Id: Ic3f636983cf6ba2796ee56e2a25b56513a4343c1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14148 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain setTimothy Pearson
Under certain conditions (training abort) BlockRxDqsLock could remain set in violation of the BKDG. Ensure BlockRxDqsLock is reset to 0 after a lane training abort. Change-Id: I1a49a24d02b2b7cacae074794ec274a424a9e66b Reviewed-on: https://review.coreboot.org/14144 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-13nb/amd/mct_ddr3: Use correct initial UI setting during DRAM trainingTimothy Pearson
Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a did not take into account the default UI setting introduced in change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM instability and occassional failure to boot. Use the correct 1UI value for the modified function semantics. Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14073 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13northbridge/intel/i3100: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i3100 boards in the chipset. Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13786 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13northbridge/intel/i82810: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i810 boards in the chipset. Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12northbridge/intel/i82830: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12nb/amd/mct_ddr3: Consolidate duplicated codeTimothy Pearson
read_dqs_read_data_timing_registers() and read_read_dqs_timing_control_registers() served essentially the same function but had slightly different semantics, causing confusion and needlessly complex Family15h code. Consolidate both into read_dqs_read_data_timing_registers() and adjust surrounding code to match new semantics. Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13994 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also rename mrccache.c -> mrc_cache.c Tested-on: boot + suspend/resume on x220 Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
The mrc_cache definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13998 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nortbridge/sandybridge/mrccache: parse the return code of flash->writeAlexander Couzens
Change-Id: I2738da99e4651598faeaa228fba447d0872e9ded Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13999 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15Timothy Pearson
Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13932 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetchTimothy Pearson
Change-Id: I4497b0be6ed6c90dbb31e89013feed8ff5ff9071 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13885 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-11nb/amd/mct_ddr3: Require minumum training quality for both read and writeTimothy Pearson
The existing MCT code proceeded to the next DRAM training phase if the minimum lane quality standard passed for either the read or write direction. Ensure that both pass for a given set of delay values before proceeding to the next training phase. Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13993 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latencyTimothy Pearson
The AMD Family 15h BKDG rev. 3.14 indicates that the maximum read latency must be calculated prior to DQS position training, however the read latency calculations use read DQS delay values that have not been set prior to DQS position training. Set the read DQS delay values to 1UI (i.e worst case) before calculating the read latency prior to DQS position training. Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13995 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Properly initialize arrays and add bounds checksTimothy Pearson
A couple of arrays were not properly initialized. This did not appear to affect operation of the codebase however it led to some ugly values being displayed when debugging was turned on. Also bounds check an array index; as before this did not appear to affect operation but was a potential point of failure. Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13934 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Restore previous DQS delay values on failed loopTimothy Pearson
Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13931 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/i945/gma: Re-enable NVRAM tft_brightnessAlexander Couzens
Commit 71512b2c (northbridge/i945/gma: fix build error with native graphics init) unintentionally changed the code to ignore the NVRAM setting `tft_brightness`. Revert that hunk to restore the original behavior. Change-Id: Iffdfc5272732bad3476f35ddac1f5a7564270531 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-09northbridge/intel/gm45: Use TSC for ramstage timer per defaultStefan Reinauer
This is a step towards isolating the timer drivers. Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13922 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
Sandy and Ivy Bridge processors use the same socket, and a mainboard with the socket can support both types of CPUs. However, they use different native graphics init code for LVDS and cause a crash if running the wrong code. This change detects the CPU type and then selects the right code to run. It will add some more code in ramstage. It also merges the {SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS. Tested on a Lenovo T520 with i7-2630qm and i7-3720qm Signed-off-by: Iru Cai <mytbk920423@gmail.com> Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91 Reviewed-on: https://review.coreboot.org/12087 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
Fill minimal info required for SMBIOS type 17. Report * DIMM size * channel * rank per DIMM * speed in Mhz * DIMM type * slot * manufacturer ID * serial Allows dmidecode to print the current RAM configuration. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Linux 4.3 * dmidecode 3.0 dmidecode output: Handle 0x0005, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Handle 0x0006, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-1-DIMM-1 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13852 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
The code can't handle cyclic zero runs. Make sure it will never wrap around by setting the top-most bit to constant one. Fixes "Mini channel test failed (2)". Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13853 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-28northbridge/intel: add missing #include guardsIru Cai
I first found the missing of #include guards when I tried to include both sandybridge/gma.h and sandybridge/sandybridge.h, but sandybridge.h includes gma.h in it and gives a compile error. Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/13775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-26nb/intel/sandybridge/raminit: Adjust timB to prevent overflowPatrick Rudolph
Improved version of I1a115a45d5febf351d89721ece79eaf43f7ee8a0 The first version wasn't well tested due to the lack of hardware and it was to aggressive. With timC being direct function of timB's 6 LSBs it's critical to match timC and timB. Some tests increments the value of timB by a small value, which might cause the 6bit value to overflow, if it's close to 0x3F. Increment the value by a small offset if it's likely to overflow, to make sure it won't overflow while running tests and bricks the system due to a non matching timC. In comparission to the first attempt, only 4 out of 128 timB values are considered bad. Needs test on real hardware ! Fixes a "edge write discovery failed" on my test system. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/13779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
Some vendors store lower frequency profiles in the regular SPD, if the SPD contains a XMP profile. To make use of the board's and DIMM's maximum supported DRAM frequency, try to parse the XMP profile and use it instead. Validate the XMP profile to make sure that the installed DIMM count per channel is supported and the requested voltage is supported. To reduce complexity only XMP Profile 1 is read. Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the default SPD. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13486 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-19nb/amd/amdmct: Add socket specific configuration for FM2Damien Zammit
Change-Id: I1088064e5f84fcabcd51e0eaaedfb5074f7fb2b5 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13709 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-02-19nb/intel/sandybridge/raminit: Improve loggingPatrick Rudolph
Use printram() in more places and use printk() only where it makes sense. Remove spamming "MRd: %x <= %x\n". Use common syntax for timing output. Change-Id: I38965967a029994112d7ab63afd4d9968a7728c5 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18nb/intel/sandybridge: Start PEG link trainingPatrick Rudolph
Issue observed: The PCIe Root port shows up in GNU/Linux but no PCIe device is being detected. Test system: * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130) * Lenovo T530 (Intel Core i5-3320M CPU) Problem description: The PEG Root port link training on Ivy Bridge needs to be manually started. Problem solution: The bits are set in early_init to meet PCIe reset timeout of 100msec. The bits should be set in PCI device enable function, but this causes the PCI enumeration to not detect the card, as it's still booting. Adding a fixed delay of 100msec resolves this problem, but this would increase boot time. Read the PCI base revision mask to make sure it's any IvyBridge CPU. Don't run the code on MRC path as it has its own PEG initilization code. Tested with: * Nvidia NVS 5400M (PCIe2) * ATI Radeon HD4780 (PCIe2) * Nvidia GeForce 8600 GT (PCIe1) Untested: * PCIe3 devices Final test results: The PEG device shows up under GNU/Linux and can be used without issues. Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/11917 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18southbridge/intel/bd82x6x: Use common gpio.cPatrick Rudolph
Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-16nb/intel/sandybridge/raminit: Add shift offsetPatrick Rudolph
It looks like the falling timing was missing the shift offset. Not sure if this was intentional, I guess not. Tested on my hardware and produced no regressions. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Please test on real hardware ! Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13682 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-11 15:12:40 +0000