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path: root/src/northbridge
AgeCommit message (Expand)Author
2016-08-09x4x: make preallocated IGD memory a cmos optionArthur Heymans
2016-08-09x4x: add non documented vram sizesArthur Heymans
2016-08-02amd/amdfam10: eliminate dead codePatrick Georgi
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
2016-07-31src/northbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
2016-07-27nb/intel/x4x: Fix CAS latency detection and max memory detectionDamien Zammit
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
2016-07-19nb/intel/x4x: Fix CAS latency detectionDamien Zammit
2016-07-15intel/x4x: Do not use scratchpad register for ACPI S3Kyösti Mälkki
2016-07-15intel/pineview: Do not use scratchpad register for ACPI S3Kyösti Mälkki
2016-07-15AGESA: Use common romstage ram stackKyösti Mälkki
2016-07-14nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declarationJonathan Neuschäfer
2016-07-09nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAMDamien Zammit
2016-07-07intel/sandybridge: read correct leaf for cpu familyRyan Salsamendi
2016-06-26intel/i945: Use common ACPI S3 recoveryKyösti Mälkki
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-20nb/intel/sandybridge/raminit: Use supported CASPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devicesPatrick Rudolph
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
2016-06-12nb/intel: Factor out common MRC codePatrick Rudolph
2016-06-04nb/intel/x4x: Fix unpopulated valueDamien Zammit
2016-06-04gm45: enable setting all vram sizes from cmosArthur Heymans
2016-06-04AGESA: Fix invalid use of CFG_ declarationsKyösti Mälkki
2016-05-31nb/intel/x4x: Add DMI/EP initDamien Zammit
2016-05-31Fix leaking CONFIG_VGA=yKyösti Mälkki
2016-05-17intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer
2016-05-09nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structureTimothy Pearson
2016-05-09nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15hTimothy Pearson
2016-05-08intel/pineview: Don't try to store 34 bits in 32Stefan Reinauer
2016-05-06amd/gx2 + amd/lx: Fix shift overflow issueStefan Reinauer
2016-05-05rdc/r8610: Move to src/socStefan Reinauer
2016-05-05dmp/vortex86ex: Merge northbridge and southbridge into socStefan Reinauer
2016-05-04nb/intel/sandybridge/raminit: support calling dram_freq multiple timesPatrick Rudolph
2016-05-04nb/intel/sandybridge/raminit: add additional fallbacksPatrick Rudolph
2016-05-04nb/intel/gm45: Fix native text mode initializationNick High
2016-05-02nb/amd/mct_ddr3: Only initialize ECC bits onceTimothy Pearson
2016-05-01nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15hTimothy Pearson
2016-05-01nb/amd/mct_ddr3: Stop receiver enable cycle training after window foundTimothy Pearson
2016-05-01nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0Timothy Pearson
2016-05-01nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4Timothy Pearson
2016-05-01nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15hTimothy Pearson
2016-04-29nb/intel/sandybridge/raminit: fix regression "always use mrccache"Patrick Rudolph
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