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2017-03-28vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner
Some Chrome OS boards previously didn't have a hardcoded vboot configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE, etc.) selected from their SoC and mainboard Kconfig files, and instead relied on the Chrome OS build system to pass in those options separately. Since there is usually only one "best" vboot configuration for a certain board and there is often board or SoC code specifically written with that configuration in mind (e.g. memlayout), these options should not be adjustable in menuconfig and instead always get selected by board and SoC Makefiles (as opposed to some external build system). (Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for Pistachio/MIPS was never finished. Trying to enable even post-romstage vboot leads to weird compiler errors that I don't want to track down now. Let's stop pretending this board has working Chrome OS support because it never did.) Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28AGESA: Introduce AGESA_LEGACY and its counterpartKyösti Mälkki
We define AGESA_LEGACY as an implementation of mainboard that has its romstage main completely under mainboard/ directory. We have learnt from other platforms this approach has several downsides when it comes to making platform-wide improvements. We start by creating per-family romstage.c file, which boards will gradually take into use by removing the AGESA_LEGACY Kconfig option we here apply to all of them. Change-Id: Id01931e185a023039a60af16a678de9966db8d65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18619 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-27nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timingsArthur Heymans
This is a cosmetic change. Change-Id: Iea4dd97e9d83594447427abd9f844e507b805192 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18960 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-03-24nb/intel/i945: Fix SPD dumpsPaul Menzel
Currently the `break` further down is called unconditionally as the brackets for the body of the if statement are missing. Add those. Change-Id: I34917a9877dcc882d880dedea689e1d72fe52888 Found-by: Coverity (CID 1372941: Control flow issues (UNREACHABLE)) Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18971 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-23northbridge/via/vx900: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/via/vx900. Change-Id: I04292a6b698a42a5c582eddcef7cf5a235e1a464 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17317 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-22nb/intel/i945: Fix errors found by checkpatch.plArthur Heymans
Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18704 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-21nb/x4x: Move checkreset before SPD readingArthur Heymans
It makes no sense to read SPDs if the system will reset anyway. Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17661 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-21nb/intel/x4x: Fix issues found by checkpatch.plArthur Heymans
Change-Id: Ie22b8bd5420f8c33df1866410af42ef41ad38362 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18694 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-18nb/i945/gma.c: Refactor panel setupArthur Heymans
This reuses some of gm45 code to set up the panel. Panel start and stop delays and pwm frequency can now be set in devicetree. Linux does not make the difference between 945gm and gm45 for panel delays, so it is safe to assume the semantics of those registers are the same. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet. This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. A default of 180Hz is selected for the PWM frequency if it is not defined in the devicetree, this might be annoying for displays that are LED backlit, but is a safe value for CCFL backlit displays. Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-10device/dram/ddr2: Add common ddr2 spd decoderPatrick Rudolph
Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid compilation errors. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-03-10northbridge/intel/i440bx: Align codePaul Menzel
Change-Id: Idd4127f7491524121b4b65c6fb9511e2c8159912 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18609 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09AGESA: Fix loop condition for eventlog readKyösti Mälkki
Do not evaluate AmdEventParams if AmdReadEventLog() fails. Change-Id: I2b8afe827ffe6757e64c00ab005d3bb8cc577321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18611 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-09AGESA: Log if memory training result cannot be storedKyösti Mälkki
A problem around CAR teardown time may result with missing training results at the time we want to save them. Record this in the logs for debugging purposes, it will not be possible to use S3 suspend if this happens. Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18534 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08nb/intel/nehalem/raminit.c: Refine broken commentStefan Tauner
Change-Id: Ic5c92d9a2d8bb040a04602e5da2cd37a2ae8db95 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/18052 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-08binaryPI platforms: Drop any ACPI S3 supportKyösti Mälkki
No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18501 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08AGESA fam10: Add missing includeKyösti Mälkki
The file is used for fam15. Change-Id: I7cdf238a8f7be4bf79546bcfc3c9d05bd8986e3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18635 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08AGESA: Move heap allocator declarationsKyösti Mälkki
Definitions are not part of ACPI S3 feature, nor do they require any AGESA headers so move them to a better location. Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-07nb/amd/amdht: Use variable for function namePaul Menzel
One very long line has to be wrapped to be shorter than 80 characters to satisfy the lint scripts. Note, that this gets rid of the brackets (). Change-Id: Ie98eff360ebc5b68ce496edc15eb2d9fddcac868 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-07AGESA: Add agesa_helper.h headerKyösti Mälkki
These definitions do not require AGESA.h include, and we will eventually remove agesawrapper.h files. Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-02nb/i945: Clean "Programming DLL Timings" functionElyes HAOUAS
As we drive both channels with the same speed, chan0dll and chan1dll are the same. Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/18472 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-03-02agesawrapper: Fix endless loop on bettongRicardo Ribalda Delgado
AGESA AmdInitEarly() reconfigures the lapic timer in a way that conflicts with lapic/apic_timer. This results in an endless loop when printk() is called after AmdInitEarly() and before the apic_timer is initialized. This patch forces a reconfiguration of the timer after AmdInitEarly() is called. Codepath of the endless loop: printk()-> (...)-> uart_tx_byte-> uart8250_mem_tx_byte-> udelay()-> start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); } while ((start - value) < ticks); [lapic_read returns the same value after AmdInitEarly()] Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17924 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-02Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"Daniel Kulesz
This reverts commit fec8872c9dee4411ba1a89fc8ec833a700b476c6. The commit introduced a regression which is causing MC4 failures when 8 RDIMMs are populated in a configuration with a single CPU package. Using just 4 RDIMMs, the failure does not occur. After reverting the commit, I tested configurations with 1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an Opteron 6276. The MC4 failures did not occur anymore. Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65 Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com> Reviewed-on: https://review.coreboot.org/18369 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2017-03-01nb/intel/i945: Fix sdram_enhanced_addressing_mode for channel1Elyes HAOUAS
Change-Id: I304467353bb9989f0d7e0ad7d1b632081f66b1af Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/18482 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2017-02-25nb/amd/amdmct: Remove another currently unused tableJonathan Neuschäfer
This fixes a warning that the new toolchain generates. Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18485 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-24nb/amd/amdmct: Remove two currently unused tablesJonathan Neuschäfer
This fixes warnings that the new toolchain generates. Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22intel/i945: Fix up whitespace and indentationPaul Menzel
Fix up the whitespace issues introduced in commit 39bfc6cb (nb/i945/raminit.c: Fix dll timings on 945GC). Change-Id: I3a4152866226401bc51c7fb1752aab541a4c72b0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18465 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2017-02-22nehalem/Kconfig: Rename TRAINING_CACHE_SIZE to MRC_CACHE_SIZEArthur Heymans
This is more consistent with newer Intel targets. Change-Id: I52ee8d3f0c330a03bd6c18eed08e578dd6ae284b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18371 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-02-22nb/intel/nehalem: Clean nehalem.hArthur Heymans
Remove unused definitions, prototypes and macros moslty copied from gm45. Change-Id: I076e204885baec3d40f165785cf4ae4adc9154c5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18370 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-22southbridge/amd: Add LPC bridge acpi path for Family14 and SB800Tobias Diedrich
Adds the necessary plumbing for acpi_device_path() to find the LPC bridge on the AMD Family14 northbridge with an SB800 southbridge. This is necessary for TPM support since the acpi path to the LPC bridge (_SB.PCI0.ISAB) doesn't match the built-in default in tpm.c (_SB.PCI0.LPCB). Change-Id: I1ba5865d3531d8a4f41399802d58aacdf95fc604 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18402 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-02-22nb/i945/raminit.c: Fix dll timings on 945GCElyes HAOUAS
Values based on vendor bios. TESTED on ga-945gcm-s2l with 667MHz ddr2. Change-Id: I2160f0ac73776b20e2cc1ff5bf77ebe98d2c2672 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17197 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-02-20nb/i945/raminit: sdram_set_channel_mode Test if DIMM slot 3 is populatedElyes HAOUAS
Add a test in case we have a DIMM2 not populated but DIMM3 is. Change-Id: I14f82afe03884740570838e7b2771233356c518d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/18386 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-17nb/intel/x4x: Implement resume from S3 suspendArthur Heymans
It rewrites the results of receive enable stored in the upper nvram region, to avoid running receive enable again. Some debug info is also printed about the self-refresh registers. (Not enforcing a reset here, since 0 does not necessarily mean it's not in self-refresh). Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17998 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17nb/intel/x4x: Fix raminit on reset pathArthur Heymans
Previously the raminit failed on hot reset and to work around this issue it unconditionally did a cold reset. This has the following issues: * it's slow; * when the OS issues a hot reset some disk drives expect their 5V power supply to remain on, which gets cut off by a cold reset, causing data corruption. To fix this some steps in raminit must be ommited on the reset path. This includes receive enable calibration. To achieve this it stores receive enable results in RTC nvram for them to be rewritten on the resume path. Note: The same thing needs to be done on the S3 resume path. Calling a hot reset after raminit "outb(0x6, 0cf9)" works. Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18009 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-14nb/i945/gma.c: Remove writes to FIFO Watermark registersArthur Heymans
Those are the result from tracing what linux or the option rom do but are not needed here. TESTED on Thinkpad X60. Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18294 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-12nb/i945/gma.c: Change name and type of mmiobase in functions argumentArthur Heymans
Void pointer arithmetics are forbidden in standard C but GCC has an extension that allows it. Change-Id: I43029b2ab2f7709b8e1ba85eb05c31341b8ac16f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18293 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-10ddr3 spd: move accessor code into lib/spd_bin.cPatrick Georgi
It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-10ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()Patrick Georgi
Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-04Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implementedArthur Heymans
This also selects RELOCATABLE_RAMSTAGE and CACHE_RELOCATABLE_RAMSTAGE_OUTSIDE_CBMEM by default on Haswell. Change-Id: I50b9ee8bbfb3611fccfd1cfde58c6c9f46b189ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18232 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-04drivers/intel/gma/vbt: Add Kconfig symbol for SSC refNico Huber
The selection of the SSC reference frequency for LVDS was based on a completely unrelated clock. The `ssc_freq` flag should be set when the SSC reference runs at a different frequency than the general display reference clock (DREF). For most platforms, there is no choice, i.e. for i945 and gm45 the SSC reference always differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's the same frequency for SSC/non-SSC (120MHz). The only, currently supported platform with a choice seems to be Pineview, where the alternative is 100MHz vs. the default 96MHz. Change-Id: I7791754bd366c9fe6832c32eccef4657ba5f309b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18186 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04nb/intel/gm45/igd: Hide IGD while disablingPatrick Rudolph
Hide the IGD to make sure ramstage doesn't detect it. Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18194 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-26amd/amdht: Fix format security errorsPaul Menzel
Ubuntu’s default compiler flags for GCC [1][2] include `-Wformat -Wformat-security`, causing errors similar like the one below. ``` CC romstage/northbridge/amd/amdht/ht_wrapper.o src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify': src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security] printk(log_level, event_class_string_decodes[evtClass]); ^ […] ``` Fix that, by explicitly using a format string. TEST=Built and booted on ASUS KGPE-D16. [1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-string-literal-and-no-format-arguments-werror-for "fprintf, error: format not a string literal and no format arguments [-Werror=format-security" [2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609. Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18208 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-25nb/intel/pineview: Make preallocated igd memory a cmos parameterArthur Heymans
Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18142 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-22nb/x4x/raminit: Fix programming dram timingsArthur Heymans
The results were obtained by comparing the MCHBAR registers of vendor bios with coreboot at the same dram timings. This fixes 2 issues: * 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with 800MHz raminit failed; * 1067MHz fsb CPUs did not boot when second dimm slot was populated. TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with DDR2 667 and 800MHz dimms. Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18022 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-20nb/gm45/gma.c: Fix reported Pixel clockArthur Heymans
Change-Id: Ie1c360ac29eb30af6f4b5447add467f3c13ba211 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18180 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-19nb/amd/ddr3: Make the maximum CDD a signed valueTimothy Pearson
max_cdd_we_delta should be signed to allow for negative CDD. Found-by: Coverity Scan #1347355 Change-Id: Iaccd1021680296d169c26c25e339f83fbd7cc065 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18162 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-14amd/mct: Add default values to highest_rank_count for DDR2Timothy Pearson
The values of highest_rank_count were undefined on DDR2 systems. Explcitly define these values on DDR2 platforms. Found-by: Coverity Scan #1347338 Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18078 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-12amd/mct/ddr2: Remove orphaned Tab_TrefT_k variableTimothy Pearson
The orphaned Tab_TrefT_k causes a failure to build due to an unused variable warning on GCC 6. Remove this variable. Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-11amd/mct/ddr3: Fix unintended sign extension warningTimothy Pearson
An unintended sign extension warning was thrown by Coverity. Explicitly state the length of the constant multiplier. Found-by: Coverity Scan #1347342 Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18077 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-11amd/mct/ddr3: Avoid using uninitialized register address in ECC setupTimothy Pearson
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as a register address under certain conditions. Refactor mct_EnableDimmEccEn_D to use the explicit address of the register in all cases. Found-by: Coverity Scan #1347337 Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18079 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-11nb/i945/raminit.c: Use Makefile.inc instead of '#include rcven.c'Arthur Heymans
Change-Id: Ib86600b687c7002646ca82d5fa52121b6eafcd60 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18087 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-12 20:59:01 +0000