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2020-07-12haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig optionAngel Pons
This Kconfig symbol allows doubling the memory's refresh rate, assuming that the MRC actually cares about it. It is disabled by default except on the mainboards which explicitly enabled this setting in `pei_data`. Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Factor out `max_ddr3_freq`Angel Pons
All mainboards choose the maximum speed of DDR3-1600. Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43120 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Compute disabled channel masks at runtimeAngel Pons
All mainboards have a non-zero SPD address to implemented DIMM slots. Knowing this, it is possible to compute the MRC slot population masks automatically instead of hardcoding the values on each mainboard. Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/asrock/b85m_pro4: Factor out common MRC settingsAngel Pons
These settings are the same on all boards. Since the other boards currently overwrite the struct contents, it doesn't make a difference. To ease review, the same settings will be dropped from other boards in separate commits, one board at a time. Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Relocate `mainboard_romstage_entry` to northbridgeAngel Pons
This is what sandybridge does, and if done properly allows factoring out common settings. Said refactoring will be handled in subsequent commits. Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Drop `struct romstage_params` typeAngel Pons
It only contains a pointer to another struct. Flatten it. Change-Id: Iab427592c332646e032a768719fc380c5794086b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Make `copy_spd` a weak functionAngel Pons
Instead of using function pointers, we can use weak functions. So, drop the pointer from `romstage_params`, leaving `pei_data` as the only remaining member. This will be cleaned up in a follow-up commit. Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-11nb/intel/haswell: Add `mb_late_romstage_setup` functionAngel Pons
This function is called at the end of `romstage_common`. Only one board makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call it after `romstage_common` has done nearly everything. Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11nb/intel/i945: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I5e33526a02872c14e9fa37a485d2f93dea8b088f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-10nb/amd/agesa/agesa_helper.h: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Icb98f3535f6c5f51081fc82262f6413f4b1a5733 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43261 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09nb/intel/gm45/acpi/gm45.asl: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I41a4f73df7fdd372ec7a80a41c8216c502054c39 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43262 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09nb/intel/ironlake/raminit.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09haswell: Drop GPIO indirection layersAngel Pons
This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09haswell: Turn RCBA configuration into a functionAngel Pons
Instead of passing around a pointer to an array, just write the relevant registers directly. Note that intel/baskingridge used spaces to indent line continuations and had to be replaced with tabs to quell Jenkins. Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08haswell: relocate `romstage_common` to northbridgeAngel Pons
Other platforms do this as well. It will ease refactoring on follow-ups. Change-Id: I643982a58c6f5370c78acef93740f27df001a06d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08haswell: drop unused function parameterAngel Pons
The `chipset_type` parameter is ignored. Change-Id: Ia3d217178cc9caabf232b3a59f505229cc03135f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08nb/intel/pineview/acpi: Remove unmatched comment startAngel Pons
This was silently commenting out the line after it. Change-Id: I2714090b8f99193ace420ad02e2d42b324349c9e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-08nb/intel/pineview: Convert to ASL 2.0 syntaxAngel Pons
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: Ibc0988c4c86f7ffef8692ff3cf3ebd92235156b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43168 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08nb/intel/pineview: Tidy up comments and cosmeticsAngel Pons
Remove some unneeded newlines, add some commas for consistency and relocate comments to match the code. Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08nb/intel/i945: Use ASL 2.0 syntaxAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: Ibf6904246ee47dffdb5fa2e24cc7a230f439c7e7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08nb/intel/i945/acpi: Tidy up comments and cosmeticsAngel Pons
Use C-style comments, drop unneeded newlines, add missing commas for consistency and relocate a comment to match the code. Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: I37fffb60944c35dfb5e0491bb023babfcf2c6a73 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43177 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08nb/intel/gm45: Use ASL 2.0 syntaxAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Ibb9b627de85eb09bdc977af55880366e4e49f3ac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-08nb/intel/gm45: Tidy up comments and cosmeticsAngel Pons
Use C-style comments, drop an unneeded newline, add missing commas for consistency and relocate a comment to match the code. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I3f91d1b57eb5530c8adcf5f682e73747435f0d47 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43172 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08nb/intel/x4x/acpi: Use ASL 2.0 syntaxAngel Pons
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I089f14dce6e3fdebcfdee126a2023ef028a01805 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-08nb/intel/x4x/acpi: Clean up commentsAngel Pons
Use C-style comments. Also drop some unnecessary newlines. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: Icd33a326cc7d9ead765e2b32e7dea237bd76fd4f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-08nb/intel/haswell/acpi: Update to ASL 2.0 syntaxAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43152 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08nb/intel/haswell/acpi: Fix host bridge registersAngel Pons
The host bridge register definitions haven't changed from Sandy Bridge to Haswell, according to the datasheets. However, coreboot's ACPI code is not the same. Looks like Haswell values are wrong, so correct them. Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-06nb/intel/i440bx: Add PMCR register to ACPI codeKeith Hui
p3b-f suspend code is going to use it. Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41092 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06nb/intel/i440bx: Refactor ACPI codeKeith Hui
Bring DRB7 OpRegion and top-of-memory indicator inside NB device. Use more concise ASL 2.0 syntax for TOM calculations. Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-02nb/intel/ironlake: Clean up code style (except raminit)Angel Pons
Reflow lines, correct coding style and align struct members, among other things. As raminit is very large, handle it on a follow-up. Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change. Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42701 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01nb/intel/ironlake/northbridge.c: Drop thunk functionsAngel Pons
Just call the called function directly. Change-Id: I0c997a63cbbd2b1029f94c23685847df910f8a0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake: Drop copy-pasted and unused macroAngel Pons
Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I78856707864563e392626a494f0e77eec9802002 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake: Use `pci_update_config32()`Angel Pons
Change-Id: I7d36165e61e6399458479d47a33fe708eba7ea86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake: Simplify BAR handlingAngel Pons
Currently, northbridge BARs are 32-bit values. We don't have any use case for BARs above 4 GiB in early stages, so handling possibly 64-bit values seems unnecessary, which currently is a noisy way to write zero. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake/ironlake.h: Clean upAngel Pons
Align values and drop copy-pasted, wrong and unused definitions. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I44f96982c8a38e1933cd78a976e18a8a11fb4096 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake: Drop copy-pasted and dead codeAngel Pons
This function was copy-pasted, comments included, from Sandy Bridge. However, it is only called with 0x0044 as the northbridge's PCI ID. Therefore, `bridge_silicon_revision() & BASE_REV_MASK` will always evaluate to 0x40, which never equals `BASE_REV_SNB`, that is, 0x00. As the condition is always false, treat this code as dead and drop it. Following a similar reasoning, all direct comparisons against SNB steppings will always be true, because `bridge_silicon_revision()` returns at least 0x40 which is always larger than either `SNB_STEP_D0` or `SNB_STEP_D1`. So, drop all but the code path that is actually used. Change-Id: I5219a6af3df98ed77c9c4abfb9a63c2ebf8171bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake: Remove unused structsAngel Pons
These were copied from gm45, but are not used. Drop them. Change-Id: I85ca37516272a2c1af88a65df2682e92d7579050 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/pineview: Drop undefined function declarationAngel Pons
This function isn't defined anywhere for Pineview. Drop its declaration. Change-Id: I38a01d6ba5aaa91de08702c1eb8a2e8c70688192 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-27sb/intel/i82801ix: Use pmutil.h definitionsAngel Pons
Also drop now-redundant definitions and include headers where needed. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I3ddd133a4e81a7f6ce9c33ce227b40006a0d1850 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42658 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22nb/intel/sandybridge/gma.c: Remove useless if conditionEvgeny Zinoviev
There's a useless check with both branches doing the same: enabling RC6 and disabling RC6p. In past, this condition would enable RC6p in IVB but not on SNB. Then, at some point, RC6p was considered unstable and was disabled, but the condition remained. It's not needed so let's remove it. Change-Id: I926bb682d1b9d21185048224490b966c33204b6a Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22device/smbus_host: Declare common early SMBus prototypesKyösti Mälkki
Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22nb/intel/haswell: Use 16-bit ops on PCI COMMANDAngel Pons
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops to update it. Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-15i945 boards: Factor out MAX_CPUSAngel Pons
At least one mobile 945 series northbridge supports 4 threads, because the dual-core Atom 330 CPU supports Hyper-threading. Therefore, we use that as the default for this chipset. Change-Id: I899ed1644d9b2da4fc72f09233a421200770110d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41845 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15x4x boards: Factor out MAX_CPUSAngel Pons
LGA775 CPUs can have at most 4 threads, and Eaglelake supports them. As this socket is also used by other chipsets, temporarily place this symbol into the northbridge scope until all chipsets are factored out. Change-Id: I6e01363d995e135815cc70779e0cd5baf806cf60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-12nb/intel/i945/rcven.c: Correct commentAngel Pons
The offset between registers has to be between different channels. Change-Id: Ic6d959c31c78073a3ecbf7a17dfb73ac36340599 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-12nb/intel/i945: Clean up raminit coding styleAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I17739a9663d809647c22c415a0998edb61c04484 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10nb/intel/i945: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I181f69372829cf712fd72887b5f2c7134bfcf15a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42190 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10nb/intel/x4x: Drop unused `pci_ops.h` includeAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change. Change-Id: I58162865d596574b8a52447624f0102b8dceefa4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42156 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10nb/intel/pineview: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: Idd6a11e95669f0a8fe9bd52359a9822b524c878c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42192 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 05:15:34 +0000