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2014-03-01intel/sandybridge: add PCI IDs for 6-Series PCHChris Douglass
The PCI ids are taken from: Intel® 6 Series Chipset and Intel® C200 Series Chipset Specification Update – NDA October 2013 CDI / IBP#: 440377 Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5226 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-24intel/*/acpi: Increase range length of MCHBAR buffer to 32 kBPaul Menzel
Linux kernel 2.6.31 reports the warning below on Intel Ivy Bridge (with FSP). resource map sanity check conflict: 0xfed10000 0xfed17fff 0xfed10000 0xfed13fff pnp 00:01 Since Sandy Bridge the length of the MCHBAR is 32 kB and it is already used that way in other places. $ more src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl […] OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) […] So instead of 16 kB specify that 32 kB are decoded in that memory range for Intel Sandy Bridge, Ivy Bridge and Haswell. (Linux kernel 3.10 does not warn about that.) Change-Id: Ie7a9356d9051c807833df85e4a806e5a9498473f Reported-by: Norwich in #coreboot on <irc.freenode.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5192 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Werner Zeh Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-02-20nehalem: Make SPD address map into parameter.Vladimir Serbinenko
It's mobo dependent. Change-Id: I7a9ba0fb7374a61178e9282acd8f10098435f1fd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5253 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-20nehalem/raminit: Fix typo of NUM_CHANNELS instead of NUM_SLOTS.Vladimir Serbinenko
Change-Id: I0fbfa8cb39881782bec3af5e43ff3c63dd2e4919 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5276 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-17sandy/ivy: Fix mrc.cache file in CBFSKyösti Mälkki
The file was not recreated when configuration changed. One would hit this bug when turning CHROMEOS on/off. Also do not create mrc.cache with CHROMEOS at all. Change-Id: I5b0ecde66589396b24967ce289bf65e20bb08825 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5211 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-16haswell: backup the default SMM region on resumeAaron Durbin
Haswell CPUs need to use the default SMM region for relocating to the desired SMM location. Back up that memory on resume instead of reserving the default region. This makes the haswell support more forgiving to software which expects PC-compatible memory layouts. Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-13Eliminate some ASL warningsOskar Enoksson
The ASL compiler warned about "Control Method should be made Serialized (due to creation of named objects within)". This commit eliminates the warnings by changing those NonSerialized into Serialized. Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5189 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-11Move hexdump32() to lib/hexdump.Kyösti Mälkki
Needs printk and is not a console core function. Change-Id: Id90a363eca133af4469663c1e8b504baa70471e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5155 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06MTRR: Mark all prefetchable resources as WRCOMB.Vladimir Serbinenko
Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28x86: add common definitions for control registersAaron Durbin
The access to control registers were scattered about. Provide a single header file to provide the correct access function and definitions. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted using this infrastructure. Also objdump'd the assembly to ensure consistency (objdump -d -r -S | grep xmm). Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172641 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4873 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-24nb/sandybridge: Move MRC cache above mrc.binAlexandru Gagniuc
This small change greatly reduces CBFS fragmentation. There is now a small gap of only 728 bytes between mrc.bin and mrc.cache, with the 64 KiB alignment maintained for mrc.cache -- assuming systemagent-r6 is used. The gap was just under 64 KiB before. With this change, it is easier to accommodate fallback and normal boot stages without having to manually place the stages in the highly fragmented CBFS. Change-Id: Ia2340c1928ed6e232949e053d1943c2f5737f741 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4763 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-23nehalem: Fix SMRAM register addressVladimir Serbinenko
Change-Id: If6646853039d15d6ba0fcf2b9b9b0658004be6e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4787 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23X201: Move early nehalem S3 magic to right place.Vladimir Serbinenko
This MCH magic needs to be done before GPIO. Now S3 (Suspend-to-RAM) works on X201. Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4632 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23nehalem: Restore frequency ratio registers on S3 resumeVladimir Serbinenko
Previously registers 274/265 and 6dc/6e8 were recomputed which lead to a slightly different values. On S3 resume it needs to be a perfect match. Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23nehalem: Small cleanup to raminit RE bindingsVladimir Serbinenko
Change-Id: Ifd3f172a1c8a108909d1a7dae94f926b2778c2b1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4633 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23nehalem: Move mrc.cache to 0xfffe0000.Vladimir Serbinenko
On nehalem there is no MRC.bin. To avoid excessively fragment the CBFS, put MRC.bin as high as possible. Change-Id: Ia3f7aef5a1e62a42c9fa9ea0f6eec2b29eb6722d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4708 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__Vladimir Serbinenko
Change-Id: I93351a2716cd58c2006400cecca1390b1704e94b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4603 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-22CBMEM: Replace cbmem_initialize() with cbmem_recovery()Kyösti Mälkki
The replacement function confirms CBMEM TOC is wiped clean on power cycles and resets. It also introduces compatibility interface to ease up transition to DYNAMIC_CBMEM. Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4668 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-21sandybridge/igd: Add brightness register descriptionsVladimir Serbinenko
Needed for brightness control for Lenovo X230 Change-Id: Ib6d127d2e050671dd402c31af06ff4726f65156c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4618 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-01-15Intel (sandy/ivy): Avoid calling cbmem_initialize() twiceKyösti Mälkki
Delay the copying of MRC cache data from CAR to CBMEM until after sdram_initialize() returns and cbmem_initialize() completes. Calling cbmem_initialize() twice would complicate the decision logic of when CBMEM area needs to be wiped clean. Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4666 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15CBMEM intel: Define get_top_of_ram() once per chipsetKyösti Mälkki
Only have one definition of get_top_of_ram() function and compile it using __SIMPLE_DEVICE__ for both romstage and ramstage. Implemented like this on intel/northbridge/gm45 already. This also adds get_top_of_ram() to i945 ramstage. Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15sandybridge: Allow skipping mrc.cacheVladimir Serbinenko
On X230 MRC fails if cache is passed to it. Until better solution is found do not create mrc.cache Change-Id: I7e70ebe3c4879e7ab33a9c95a0c9e40408ff5ca4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4680 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-13lib: Make log2() available in romstage on ARM, not just x86Alexandru Gagniuc
On x86, log2() is defined as an inline function in arch/io.h. This is a remnant of ROMCC, and forced us to not include clog2.c in romstage. As a result, romstage on ARM has no log2(). Use the inline log2 only with ROMCC, but otherwise, use the one in clog2.c. Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4681 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12sandybridge: Use calls rather than asm to call to MRC.Vladimir Serbinenko
Using asm as it's done currently is unsafe because caller-saved registers are not declared as clobbered. Using real call is nicer. regparm((1)) ensures that argument is passed in %eax as expected. Change-Id: I7449182582eaa53d4e473bc834b472edd8ee0d30 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_fileVladimir Serbinenko
Number one reason to use cbfs_get_file was to get file length. With previous patch no more need for this. Change-Id: I330dda914d800c991757c5967b11963276ba9e00 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4674 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-10Replace all occurences of sprintf with snprintfVladimir Serbinenko
THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-06MRC cache: determine flash size on runtimeVladimir Serbinenko
It should be possible to put coreboot compiled for smaller chip by putting it at the end of bigger chip. We already have chip size in flash->size. Use it. Tested on Lenovo X230. Change-Id: If8ff03ed72671a9f2745ed4e759a04e83aa7cc37 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4612 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-04X201: Fix native video initVladimir Serbinenko
Due to recent restructuring X201 native video init has disappeared from config options. Put it back and fix compilation with it. Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4606 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8 (rev F): Move rev F0/F1 workaround to headerKyösti Mälkki
Place this in header so it works also when raminit_f.c and raminit_f_dqs.c are not #included in romstage.c build. The workaround remains to be disabled for all boards. Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4568 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridgeKyösti Mälkki
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORTKyösti Mälkki
Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD K8 (rev-F): Always have RAMINIT_SYSINFOKyösti Mälkki
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO, so have the option enabled together with K8_REV_F_SUPPORT. Also move the option under AMD K8. Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD K8: Socket implies K8_REV_F_SUPPORTKyösti Mälkki
K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1). Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4557 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-27via: Write »access« without »m« at endPaul Menzel
The comment was copied around so fix all occurrences using the following command. $ git grep -l accessm | xargs sed -i 's/accessm/access/g' Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4577 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD fam10: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4555 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-23usbdebug: Add option to disable console for romstageKyösti Mälkki
If there is trouble setting up usbdebug, it may be useful to delay usbdebug init to run in ramstage. Change-Id: I31de5a06d3f9ce19f71c422cce0c8cb0fd50f396 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4488 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-21haswell: add option to change DqPinsInterleavedStefan Reinauer
Some mainboards will need to have this set. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0 Reviewed-on: https://gerrit.chromium.org/gerrit/65722 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell: Misc updates from 1.6.1 ref codeDuncan Laurie
These programming sequences were changed in the latest code. Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add a specific post code for S3 resume failuresDuncan Laurie
If the firwmare is flashed and the MRC cache is blown away then it is not possible to resume. Right now this can be inferred from the event log but it can be made very clear by adding a unique post code for this event. 1) boot falco 2) flash firmware 3) suspend and then resume 4) check for post code 0xef in log 0 | 2013-08-08 16:27:47 | Log area cleared | 4096 1 | 2013-08-08 16:27:47 | ACPI Enter | S3 2 | 2013-08-08 16:27:55 | System boot | 48 3 | 2013-08-08 16:27:55 | Last post code in previous boot | 0xef | Resume Failure 4 | 2013-08-08 16:27:55 | System Reset 5 | 2013-08-08 16:27:55 | ACPI Wake | S5 Change-Id: I7602d9eef85d3b764781990249ae32b84fe84134 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65259 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell: Add pei_data field for USB routingDuncan Laurie
The linux kernel will unconditionally route all USB ports to the XCHI controller at boot. The EHCI controller can then be disabled, and it should be left disabled by the reference code when this is done. However not all OS may do this unconditional route, so provide an option to the reference code binary to enable this behavior. Change-Id: Iedf5af54182bf109cd1119c1999e46300665d41e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63797 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4403 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-12HDA: Enable Mini-HDA and fix up PCH-HDA initDuncan Laurie
The SystemAgent contains a mini-hd audio controller at PCI 0:3.0 which uses the same verb table init sequence as the southbridge. In order to avoid two copies of the verb table loading code I separated out the HDA verb table functions into a file that can be re-used and then added a minihd driver to the haswell northbridge. The minihd verb table is the same across devices so it can live within the minihd driver rather than needing to be specified in each separate mainboard. I also fixed up the driver for lynxpoint HDA by following the reference code. Without HDMI cable plugged in driver does not find any codec, and it does not seem to re-probe when HDMI is connected. We may be missing kernel patches for this. hda-intel 0000:00:03.0: no codecs found! With a basic kernel patch to add 0x0a0c device ID to HDA driver and with HDMI cable connected it is much happier: snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9 snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10 input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11 Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4318 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12haswell: Fix up GPU power management setupDuncan Laurie
New/more magic values from latest ref code. Change-Id: Ia2655333b4daca86c2f2a76f5edcd55cdaf3f851 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61334 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4356 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12haswell: Export functions for CPU family+model and steppingDuncan Laurie
These are needed to enable workarounds/features on specific CPU types and stepping. The older northbridge function and defines from sandybridge/ivybridge are removed. Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61333 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4355 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-07haswell: Add ACPI support for Controllable TDPDuncan Laurie
Add ACPI Methods to enable and disable power limiting with PL1. This can be used in ACPI Thermal Zone or in EC ACPI _QXX events. This commit adds new unused methods and is fully tested with the subsequent commit that makes use of these methods. Change-Id: I9d8d23bfe9cf7c756ff8ab0412e5a010826b12db Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60546 Reviewed-on: http://review.coreboot.org/4334 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
1) fix enable of power aware interrupt routing 2) set BIOS_RESET_CPL to 3 instead of 1 3) mirror PKG power limit values from MSR to MMIO on all SKUs 4) mirror DDR power limit values from MMIO to MSR 5) remove DMI settings that were from snb/ivb as they do not apply to haswell 1) verify power aware interrupt routing is working by looking in /proc/interrupts to see interrupts routed to both cores instead of always to core0 BEFORE: 58: 4943 0 PCI-MSI-edge ahci AFTER: 58: 4766 334 PCI-MSI-edge ahci 2) read back BIOS_RESET_CPL to verify it is == 3 localhost ~ # iotools mmio_read32 0xfed15da8 0x00000003 3) read PKG power limit from MMIO and verify it is the same as the MSR value localhost ~ # rdmsr 0 0x610 0x0000809600dc8078 localhost ~ # iotools mmio_read32 0xfed159a0 0x00dc8078 localhost ~ # iotools mmio_read32 0xfed159a4 0x00008096 4) read DDR power limit from MSR and verify it is the same as the MMIO value (note this is zero based on current MRC input) localhost ~ # rdmsr 0 0x618 0x0000000000000000 localhost ~ # iotools mmio_read32 0xfed158e0 0x00000000 localhost ~ # iotools mmio_read32 0xfed158e4 0x00000000 Change-Id: I6cc4c5b2a81304e9deaad8cffcaf604ebad60b29 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60544 Reviewed-on: http://review.coreboot.org/4333 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
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