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2016-11-08nb/x4x/raminit.c: Improve crossclock table cosmeticsArthur Heymans
Change-Id: I3f692c55fdff99aa9eb41eaaea79a41ac93be590 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17170 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08intel/e7501: Remove unused northbridge codeKyösti Mälkki
No boards left in the tree for this northbridge. Change-Id: Id45da11b9d78cbd6bd50acb5a3c6c3c270f9020e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17281 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07amd/pi/hudson: Move audio to northbridgeMarshall Dawson
Carrizo (00660F01), Merlin Falcon (00660F01), and Stoney Ridge (00670F00) locate the HD audio controller on the northbridge root complex at 9.2 instead of the FCH. This duplicates the existing ASL into the northbridge directories and reports the correct address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f68206c2b42c90076efd968a99f4d3a49e403438) Change-Id: I6d42bb40ad58c7f35e8c88ff27ebd327d656c021 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17216 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07pci_ids.h: Correct recent AMD ID namesMarshall Dawson
Adjust the names to match AMD's convention for family and model. This patch is relevant for: Trinity & Richland: Family 15h Models 00h-0Fh Carrizo: Family 15h Models 60h-6Fh Mullins & Steppe Eagle: Family 16h Models 30h-3Fh Change-Id: I613b84ed438fb70269d789c9901f1928b5500757 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17169 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2016-11-02nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"Elyes HAOUAS
Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17192 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02northbridge/amd: Modify 00670F00 chip.h to match DCTMarshall Dawson
The Stoney device supports only a single channel of DRAM with two DIMMs. Correct the dimmensions of the SPD lookup array. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: <marcj303@gmail.com> (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8) Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02northbridge/amd: Update 00670F00 asl for reduced hardwareMarshall Dawson
Remove the language associated with the Carrizo Gfx PCIe bridges. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748) Change-Id: I8b67a646f98667d500fcee5da8389c10483488da Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17144 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02northbridge/amd: Update all names and IDs for 00670F00Marc Jones
Modify the new Stoney support files to match the APU's IDs and codename. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit de626730758def76e558294762a06d8ec9950cb9) Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17143 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02northbridge/amd: Copy 00660F01 directories to 00670F00Marc Jones
Prepare for new 00670FF00 (StoneyRidge) support. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 037cf16883fafd329a15f903ddf97e24a879bcce) Change-Id: I130d4f13beb2c1d71e4e4e9be5011f7993b34660 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02nb/i945/gma.c: use an if else statement for use of native initArthur Heymans
Change-Id: I1e964ed939ca5282008253e3fbdd1d2fa5cbf278 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17076 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-02nb/i945/gma.c: Do not try to load vbios when selecting native initArthur Heymans
This fixes a typo introduced in 9c5fc62f: "nb/i945/gma.c: use IS_ENABLED instead of #if, #endif". Change-Id: I2c9ca796767a507483c32867f9b7f172842a1ab3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17075 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-29nb/intel/sandybridge/gma: Always initialize DP buffer translationNico Huber
These settings should be always made by the firmware, no matter if we set up graphics or not. It looks like Linux doesn't even know these registers. The values are taken from the PRMs for Sandy Bridge and Ivy Bridge [1, 2]. They match the settings that were done in the native graphics path for Ivy Bridge. I expect the differences to be an update (i.e. the set- tings we did on the Sandy Bridge path were just outdated). Also, these settings affect the PCH and not the CPU which are independent from each other. [1] Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 3 Part 3: PCH Display Registers (SandyBridge) Doc Ref #: IHD-OS-V3 Pt3 – 05 11 https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part3.pdf [2] Intel ® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 3 Part 4: South Display Engine Registers (Ivy Bridge) Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part4.pdf Change-Id: I83cc90c7558b93273a727f332fb0d8ced47ed70e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17073 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-29nb/intel/i945/gma.c: Homogenize code for PCI IDs.Elyes HAOUAS
Change-Id: Ic01565cb730c49a5fe77c8f4990276970964f101 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17174 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-10-26nb/x4x/gma.c: Remove writes to DP, FDI registersArthur Heymans
Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17111 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-26nb/gm45/gma.c: Remove writes to DP, FDI registersArthur Heymans
Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17110 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-26nb/intel/i945: Add PCI id for I945GCNico Huber
Also drop an odd comment about the resource allocator which seems to work fine, with the right id. Change-Id: I9099211fe946c28f90dd7730345b81a3f7f6f545 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17095 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-25nb/i945/gma.c: Set the MSAC register correctlyArthur Heymans
This fixes an instability on 945gc where the IGD completely locks up the system, when for instance tasked to do something with compositing (like GNOME or GDM). TESTED on ga-945gcm-s2l and d945gclf TEST: launch GDM (gnome display manager) Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17094 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-10-24nb/i945/Kconfig: select the correct VGA_BIOS_ID for 945GCArthur Heymans
Change-Id: I48ae27c5460020b9118e6ade1a3e610b542999c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17040 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19nb/i945/gma.c: use IS_ENABLED instead of #if, #endifArthur Heymans
Change-Id: Ib58126e1c9001ed679e161d6d06241fac762bdb3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17049 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPUArthur Heymans
The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect. The result is that 800MHz FSB CPUs now properly work with 667MHz RAM. Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas Elyes. Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17038 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19nb/i945/raminit: Add fix for 1067MHz FSB CPUsArthur Heymans
Previously the 945gc raminit only worked for 533MHz FSB CPUs. This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are taken from the vendor bios of Gigabyte ga-945gcm-s2l. The result is that 1067MHz FSB CPUs now boot without problems. 800MHz FSB cpus still don't get past romstage. Change-Id: I13a6b97d2e580512155edf66c48405a153121957 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17034 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19nb/gm45,x4x/gma.c remove writes to nonexisting FDI registersArthur Heymans
This removes writes to FDI related registers since there is no FDI link on these targets. This is likely a remainder from copying code from later targets. TESTED on Thinkpad x200 (gm45) Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16993 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-19nb/i945,gm45,x4x/gma.c: fix unsigned arithmeticsArthur Heymans
This issue was found by Coverity Scan, CID 1364118. Change-Id: Iba3c0f4f952729d9e0987d928b63ef8b8fe8841e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16992 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-19nb/gm45,x4x/gma.c: Compute p2 in VGA init instead of hardcoding itArthur Heymans
According to: "Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller PR" the p2 divisor needs to be 10 when the dotclock is below 225MHz and 5 when its above 225MHz. Change-Id: I363039b6fd92051c4be4fdc88788f27527645944 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16991 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-18northbridge/via/vx800: Convert 'for (;;)' to 'die'Elyes HAOUAS
Change-Id: I3f99190401d8df1415328da9c3b928194593901c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16989 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-15nb/i945/gma.c: correct VSYNC end offsetArthur Heymans
According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" the VSYNC end should start at bit 16. This is also how Linux (at least 4.4) sets this register, which can be seen with intel-gpu-tools. TESTED on Lenovo thinkpad X60 (it does not change anything). Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17015 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-12i945/gma.c: Only init LVDS if it is detectedArthur Heymans
Some devices have no LVDS output but if no VGA is connected or no EDID can be found, it will try to init LVDS. This patch detects the presence of an LVDS panel and makes sure that LVDS is not initialized when it is absent. Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16513 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11nb/gm45/gma.c: use linux code to compute LVDS dotclock divisorsArthur Heymans
This reuses linux code (at least 4.1) to compute the graphic clock divisors for LVDS displays on the gm45 northbridge. The divisors m1, m2, n, p1, p2 need to be such that "BASE_FREQUECY * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / (p1 * p2)" is as close as possible to the target_frequency. On g4x hardware the BASE_FREQUENCY is 96000kHz. This potentially increases LVDS display compatibility. Change-Id: I2323af5756431e89769f95059790f5a922af14b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16741 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-11nb/intel/*/graphic_init: use sizeof instead of hardcoding edid sizeArthur Heymans
Change-Id: I2b8c4ef75cca9f9d5251789cda4187a02076b69d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16964 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11i945/raminit.c: correctly write CLKCFG for 945GCArthur Heymans
MHCBAR(CLKCFG) was previously incorrectly written by the sdram_program_memory_frequency function which required falsely limiting the max dram frequency for 945GC. TESTED on Intel d945gclf (memclock 667 and fsb 533) and Gigabyte ga-945gcm-s2l (memclock 667 and fsb 1067) Change-Id: I520efd69fa09fc9fde87c5301fd81121fde6a700 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-10-11cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZENico Huber
An epic battle to fix Nehalem finally ended when we found an odd mask set in SMRR. This was caused by a wrong calculation of TSEG size. It was assumed that TSEG spans the whole space between TSEG base and GTT. This is wrong as TSEG base might have been aligned down. TEST: On X201, copied 1GiB from usb key to sd-card and verified. Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7 Found-by: Alexander Couzens, Nico Huber Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16939 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-10intel/i945: Use "IS_ENABLED" for fsbclk & memclkElyes HAOUAS
Change-Id: I3213a8664955239b10bcf1784ce1ba5e0d95688b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16958 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-10-10x4x/gma.c: Add VESA native resolution modeArthur Heymans
This patch implements native resolution, VESA mode, on the VGA output of x4x. It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ 60Hz) if this is no EDID could be found. This fallback mode only works in textmode since in VESA mode some payloads (grub2) rely on VBE info, which is being generated from an EDID. Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16498 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10northbridge/intel/nehalem: Remove commented codeElyes HAOUAS
Change-Id: I2d40049a27f725f14acbc16438f0e6ea7cdd7329 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16879 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10northbridge/intel/i440bx: Remove commented codeElyes HAOUAS
Change-Id: I0dd8c32f1b9165fe8c449cee1c21a155a725c04f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16878 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09src/northbridge/via: Remove commented codeElyes HAOUAS
Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16898 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family15*: Remove commented codeElyes HAOUAS
Change-Id: If372655700c18340d51368a39392560f664f4a45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family14: Remove commented codeElyes HAOUAS
Change-Id: I04fe6b7a8798d0f3cb54130283ce5a50eb9ac5b4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16895 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdk8: Remove commented codeElyes HAOUAS
Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16893 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/lx: Remove commented codeElyes HAOUAS
Change-Id: I37c1674ee380936aba797e24897593fcca3b0269 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16891 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/pi/00730F01: Remove commented codeElyes HAOUAS
Change-Id: I930c761b9a2422590af3a0a5008b4ff2abe3fd96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16890 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdmct/mct_ddr3: Remove commented codeElyes HAOUAS
Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16889 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family16kb: Remove commented codeElyes HAOUAS
Change-Id: Ic22f8a00e6009e104df8c4374067369ebbf90ee2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16888 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family15rl: Remove commented codeElyes HAOUAS
Change-Id: I5f45a4cd5661140f57aa37e86cc8a34622da3de5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16887 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family10: Remove commented codeElyes HAOUAS
Change-Id: I7966f996a4291cc6b97b53aba59b43358de94e45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16886 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdfam10: Remove commented codeElyes HAOUAS
Change-Id: I63fee62253cb0488a041c9985a646102261b8c5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16880 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/northbridge: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04nb/gm45: allow use of 352M preallocated ram for igdArthur Heymans
The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family" mention the possibility of having 352M ram preallocated for the integrated graphic device. This only worked fine if the amount of ram in the system was 3GB or less. When 4G or more is installed, memory is remapped to create a 1GB large pci mmio hole which is not enough and creates conflicts when 352M vram is used. This patch increases the pci mmio hole size on Lenovo x200 to allow 352M vram to work. TEST: build and flash on target with 4GB ram or more, use nvramtool to set gfx_uma_size to 352M and reboot. Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16831 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/northbridge: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Iea0352f85f4d5f47fc906edbe625e7bbf3f03afd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16863 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-01northbridge/via/cn700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/via/cn700. Change-Id: Ib7761697daad3c459f3568e5158f925199bcd919 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16689 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 00:14:02 +0000