summaryrefslogtreecommitdiff
path: root/src/northbridge
AgeCommit message (Expand)Author
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
2016-03-11nortbridge/sandybridge/mrccache: parse the return code of flash->writeAlexander Couzens
2016-03-11nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15Timothy Pearson
2016-03-11nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetchTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Require minumum training quality for both read and writeTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latencyTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Properly initialize arrays and add bounds checksTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Restore previous DQS delay values on failed loopTimothy Pearson
2016-03-11northbridge/i945/gma: Re-enable NVRAM tft_brightnessAlexander Couzens
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
2016-03-09northbridge/intel/gm45: Use TSC for ramstage timer per defaultStefan Reinauer
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
2016-02-28northbridge/intel: add missing #include guardsIru Cai
2016-02-26nb/intel/sandybridge/raminit: Adjust timB to prevent overflowPatrick Rudolph
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
2016-02-19nb/amd/amdmct: Add socket specific configuration for FM2Damien Zammit
2016-02-19nb/intel/sandybridge/raminit: Improve loggingPatrick Rudolph
2016-02-18nb/intel/sandybridge: Start PEG link trainingPatrick Rudolph
2016-02-18southbridge/intel/bd82x6x: Use common gpio.cPatrick Rudolph
2016-02-16nb/intel/sandybridge/raminit: Add shift offsetPatrick Rudolph
2016-02-13sandybridge: Always include MRC if not using native RAM init.Vladimir Serbinenko
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
2016-02-09sandybridge: Set all native gfx-related options in northbridge code.Vladimir Serbinenko
2016-02-09ivy: Add a possiblity for mainboard early init.Vladimir Serbinenko
2016-02-09Revert "northbridge/intel/peg: Disable unused ports"Nico Huber
2016-02-05nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15hTimothy Pearson
2016-02-05nb/amd/mct_ddr3: Work around RDIMM training failureTimothy Pearson
2016-02-04northbridge/intel/peg: Disable unused portsPatrick Rudolph
2016-02-04nb/intel/sandybridge/raminit: Fix two dimms per channelPatrick Rudolph
2016-02-02src: Fix various spelling and whitespace issues.Martin Roth
2016-02-01nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resumeTimothy Pearson
2016-02-01drivers/pc80: Add PS/2 mouse presence detectTimothy Pearson
2016-01-29Revert "northbridge/intel/sandybridge: Fix random raminit failures"Vladimir Serbinenko
2016-01-29nb/amdmct/mct_ddr3: Enable mainboard voltage setTimothy Pearson
2016-01-29cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systemsTimothy Pearson
2016-01-29nb/intel/x4x: Move to early cbmemDamien Zammit
2016-01-29nb/intel/x4x: Cleanup gma.cDamien Zammit
2016-01-29nb/intel/x4x: Tidy up raminit and fix msbpos() functionDamien Zammit
2016-01-29nb/intel/x4x: Tidy up northbridgeDamien Zammit
2016-01-29nb/intel/x4x: Fix memory hole with both channels populatedDamien Zammit
2016-01-28via/cx700: Use zeroptr over 0Patrick Georgi
2016-01-28nb/intel/pineview: Native VGA init (CRT)Damien Zammit
2016-01-26nb/intel/pineview: Increase MMCONF decoding to 256 bussesDamien Zammit
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 00:41:20 +0000