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AgeCommit message (Expand)Author
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining placesFelix Held
2018-08-01sandybridge/raminit_common: use macro for execute command queue registerFelix Held
2018-08-01sandybridge/raminit_common: use FOR_ALL_CHANNELS macroFelix Held
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-08-01northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held
2018-08-01nb/intel/gm45: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/pineview: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/sandybridge: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
2018-07-30northbridge/nehalem: add MCHBAR AND/OR/AND_OR macrosFelix Held
2018-07-30northbridge/nehalem: clean up header fileFelix Held
2018-07-29sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held
2018-07-29sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
2018-07-29nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
2018-07-26nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus widthPatrick Rudolph
2018-07-26nb/intel/sandybridge/raminit: Fix PDWN_mode on desktopsPatrick Rudolph
2018-07-26nb/intel/nehalem: Remove the C native graphic initArthur Heymans
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
2018-07-25nb/intel/sandybridge/raminit: Fix non ASCII charPatrick Rudolph
2018-07-25nb/intel/sandybridge/raminit: Set REFIx9 according to specPatrick Rudolph
2018-07-23AGESA binaryPI: Remove code for CONFIG_CBB!=0Kyösti Mälkki
2018-07-20AGESA binaryPI: Fix and optimize for MAX_NODES_NUMKyösti Mälkki
2018-07-12nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMsElyes HAOUAS
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
2018-07-02src/nb: Fix non-local header treated as localElyes HAOUAS
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
2018-06-29sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans
2018-06-23nb/intel/i945: Remove dead codeElyes HAOUAS
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
2018-06-20nb/intel/e7505: Leave ROM as un-cacheable in postcarKyösti Mälkki
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-17nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
2018-06-17nb/intel/nehalem: Fix DEVEN definesPatrick Rudolph
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
2018-06-14nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
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