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2016-12-08nb/intel/sandybridge: Lock PAVPCDennis Wassenberg
This makes CHIPSEC happy. We don't enable PAVP, but it shouldn't hurt to lock it nevertheless. Change-Id: I9428f0b6e8868832eb79f7aea24cbc7961c2aa8f Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Reviewed-on: https://review.coreboot.org/17352 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07AMD fam10 binaryPI: Remove invalid PCI ops on CPU domainKyösti Mälkki
Device is of type CPU_CLUSTER, while pci_dev_set_resources() expects PCI_DOMAIN. Change-Id: Ib1add47d71071abb6e9c28e3a85dd0b671741b71 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Drop redundant loggingKyösti Mälkki
Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17696 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
Resource allocator and 64-bit PCI BARs will need it and PCI use is not really restricted to x86. Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17689 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Remove conflicting duplicate declarationsKyösti Mälkki
The code originates from times before __SIMPLE_DEVICE__ was introduced. To keep behaviour unchanged, use explicit PCI IO operations here. Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already setKyösti Mälkki
It gets selected from CPU_AMD_MODEL10XXX. Change-Id: Iffab43edc1152b07ba2af6273d4b5eb94afe33ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17692 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Untested. Change-Id: I61ab1e5279c995f933971332673aa4ca0150e80c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17544 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Boards with this chipset do not have any reference of MMCONF_BASE_ADDRESS being written to chipset registers. Either board support is already broken or FSP takes care of this early and Kconfig lacks the notice that this parameter must match with the chosen FSP binary. CPU bootblock associated with this chipset uses exclusive PCI IO access already. Untested. Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17547 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05nb/intel/sandybridge/raminit: Split raminit.cPatrick Rudolph
Split raminit.c into smaller parts. Move all functions that will be used by chip-specific code into raminit_common.c. The chip-specific changes includes new configuration values for IvyBridge and 100Mhz reference clock support, including new frequencies. No functionality is changed. Tested on Lenovo T420. Change-Id: If7bb5949f4b771430f3dba1b754ad241a7e8426b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17604 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-03nb/i945/raminit.h: Fix fsb_frequency's commentElyes HAOUAS
Change-Id: Ie1c28b73bd2d34070173838d341cc6b8f65f50ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17686 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-03nb/x4x: Fix sticky scratchpad register offsetArthur Heymans
Change-Id: I9b952e32dc661f5c1fa96b037b415693d8777b04 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17685 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30intel/fsp_rangeley: Fix regression on MMCONF_SUPPORTKyösti Mälkki
Following commit did not move this selection to northbridge: bac0fad Remove explicit select MMCONF_SUPPORT Change-Id: I5f3c429dfd160eb439f396db2baf0ecf280022fd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17653 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-29nb/intel/nehalem,sandybridge: Hook up libgfxinitNico Huber
Change-Id: I4288193c022cc0963b926b4b43834c222e41bb0d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16953 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-29nb/intel/i945/gma: Declare count variable outside 'for' loopPaul Menzel
Building an image for the Lenovo X60 on Debian 8.5 (jessie) with GCC 4.9.2, compilation fails with the error below. ``` $ gcc --version gcc (Debian 4.9.2-10) 4.9.2 […] $ make # lenovo/x60 with native graphics initialization […] CC ramstage/northbridge/intel/i945/gma.o src/northbridge/intel/i945/gma.c: In function 'probe_edid': src/northbridge/intel/i945/gma.c:570:2: error: 'for' loop initial declarations are only allowed in C99 or C11 mode for (int i = 0; i < 8; i++) { ^ src/northbridge/intel/i945/gma.c:570:2: note: use option -std=c99, -std=gnu99, -std=c11 or -std=gnu11 to compile your code Makefile:316: recipe for target 'build/ramstage/northbridge/intel/i945/gma.o' failed make: *** [build/ramstage/northbridge/intel/i945/gma.o] Error 1 ``` Fix this by declaring the count variable outside the 'for' loop. Change-Id: Icf69337ee46c86bafc4e1320fd99f8f8f5155bfe Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17623 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-11-29nb/intel/sandybridge/raminit: Support CL > 11Patrick Rudolph
The code won't allow anything beyond CL11 due to short CAS Latency mask and a bug in mr0 which had the wrong bit set for CL > 11. Increase the CAS bitmask, fix the mr0 reg to allow CAS Latencies from CL 5 to CL 18. Use defines instead of hardcoding min and max CAS latencies. Tested on X220 with two 1866 MHz, CL13 memories Tested-By: Nicola Corna <nicola@corna.info> Change-Id: I576ee20a923fd63d360a6a8e86c675dd069d53d6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17502 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-28nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequencyArthur Heymans
This allows to set the backlight PWM frequency and the duty cycle in the devicetree instead of using a plain BLC_PWM_CTL value. Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17597 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-28nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculationNico Huber
Fix-up for 696abfc nb/intel/x4x: Fix and deflate `dimm_config` in raminit It didn't fix the channel-number shifting issue as intended. The channel index is either 0 or 1. DIMMs are counted from 0 to 3 where 0..1 covers channel 0, and 2..3 covers channel 1. Since we have two DIMMs per channel, we have to multiply the channel index by 2 (or shift it left by 1) to get the index of the first DIMM in the channel. Finally, to get the offset of a DIMM in the channel we take its index modulo 2 (again, the number of DIMMs per channel). Change-Id: I2784b0cb655bfe823bf5fa48b722623dfca1ddc3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17612 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-11-28nb/intel/gm45: Fix panel-power-sequence clock divisorNico Huber
We kept this value at it's default on the native graphics init path. Maybe the Video BIOS path, too, I don't know if the VBIOS sets it. The panel power sequencer uses the core display clock (CDCLK). It's based on the HPLLVCO and a frequency selection we made during raminit. The value written is the (actual divisor/2)-1 for a 100us timer. v2: Fix unaligned mmio access inherited from Linux. v3: Use MCHBAR8() instead. Also, the unaligned access might have worked after all. Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17619 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-11-28nb/intel/sandybridge/raminit: Reset internal state on fallback attemptsPatrick Rudolph
Some methods like discover_402x assume an clear state. Should fix fallback attempt raminit failures. Change-Id: I7a6fe044c17f5e0dbfa0e9b9d2aed0c3b6ae3972 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17471 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-26nb/intel/x4x: Fix and deflate `dimm_config` in raminitNico Huber
By shifting the `chan` right instead of left, values were always taken from the DIMMs of the first channel. The diff-stat also looks like an improvement. Change-Id: I605eb4f9b04520c51eea9995a2d4a1f050f02ecc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17587 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-11-24nb/intel/i82810: Make sure DIMM size isn't negativeMartin Roth
If smbus_read_byte returned an error when reading the DIMM size, this value would be used as an offset into an array. Check for the error, and set the DIMM size to 0 if there's a problem. Addresses coverity issue 1229658 - Negative array index read Signed-off-by: Martin Roth <martinroth@google.com> Change-Id: I6461a0fae819dd9261adbb411c4bba07520d076d Reviewed-on: https://review.coreboot.org/17485 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-23northbridge/intel/i5000: Convert 'for(;;)' to 'die'Elyes HAOUAS
Change-Id: I1ceea759a40d740503bde725ad6d72fab4aa7971 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17006 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22nb/intel/sandybridge/raminit: Do not log inside busy-wait loopKyösti Mälkki
Time spent in printk() is highly unpredictable, depending of the enabled consoles. If only CBMEM console is enabled, debugstring is repeated tens of times, consuming preram_cbmem_console storage. Change-Id: I2b0d9bd11c294d988a0eb84b90e77d5cc7f1f848 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17516 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22intel FSP sandy/ivy: Move select MMCONF_SUPPORTKyösti Mälkki
Note: Platforms have no MMCONF_SUPPORT_DEFAULT. Change-Id: I8a02ea78957fca23b1cf161a00d5e3edda73d683 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17543 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-21nb/intel: Fix some spelling mistakes in comments and stringsMartin Roth
Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17478 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-20intel sandy/ivy: Improve DIMM replacement detectionKyösti Mälkki
When MRC cache is available, first read only the SPD unique identifier bytes required to detect possible DIMM replacement. As this is 11 vs 256 bytes with slow SMBus operations, we save about 70ms for every installed DIMM on normal boot path. In the DIMM replacement case this adds some 10ms per installed DIMM as some SPD gets read twice, but we are on slow RAM training boot path anyways. Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-11-20intel sandy/ivy: Skip SPD loading on S3 resume pathKyösti Mälkki
For S3 resume path SPD is only used for DIMM replacement detection. As this detection already fails in the case of removal/insertion of same DIMM, we can rely on cbmem_recovery() failure alone to force system reset in case someone accidentally does DIMM replacements while system is suspend-to-ram stage. Skipping DIMM replacement detection allows skipping slow SPD loading, thus reducing S3 resume path time by 80ms for every installed DIMM. Change-Id: I4f2838c05f172d3cb351b027c9b8dd6543ab5944 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17490 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-20intel sandy/ivy: Move SPD loading after TS_BEFORE_INITRAMKyösti Mälkki
Take the timestamp before SPD loading takes place, for easier comparison against MRC blob performance and followup changes will optimize some of the slow SPD/SMBus operations. Change-Id: I50b5a9d02d2caf4c63e1a4025544131a085b8fb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17489 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-20intel sandy/ivy: Change CRC used to detect DIMM replacementKyösti Mälkki
Switch to use CRC of unique identifier section SPD[117..127], remaining area of SPD data is ignored. Change-Id: If4b43183f99f5f911ae6c311b43c29a72b9922e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17487 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-11-20nb/intel/sandybridge/raminit: Fix disable_channelPatrick Rudolph
Also memset info.dimm as it contains decoded SPD timings used to calculate common timings. Tested manually on Lenovo T420. Change-Id: I659e5bc2a6cbadd9539931ee00ddea0a5253295f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17473 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-20nb/intel/sandybridge/raminit: Find CMD rate per channelPatrick Rudolph
No need to find the same CMD rate for all channels. Allow different CMD rates for every channel. Tested on Lenovo T420 with different modules on each channel. No regressions found. Change-Id: I7036275ae89335dd3549ec392fa64824355b3cbf Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17472 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-20nb/intel/sandybridge/raminit: Define registersPatrick Rudolph
Use register names found on forums.corsair.com. No functionality changed. Change-Id: Ibaede39a24e8df1c4d42cb27986ab66174b7d45b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17400 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-20nb/intel/sandybridge/raminit: Get rid of fallback attemptsPatrick Rudolph
Locking the PLL again once it's locked doesn't work. The MRC doesn't do this, for some reason. Remove fallback attempts of lowering DDR frequency. Change-Id: Iccb54fa7d7357a22182dd26bd5b49c4073c04dc9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17399 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-20nb/intel/sandybridge/raminit: Fix CAS Write LatencyPatrick Rudolph
As documented in DDR3 spec for MR2 the CWL is based on DDR frequency. There's no to little difference for most memory modules operating at DDR3-1333. It might fix problems for memory modules that operate at a higher frequency and memory modules with low CL values should work even better. Tested on Lenovo T420 with DDR3-1333 CL9 and DDR3-1600 CL11. No regressions found. Change-Id: Ib90b5de872a219cf80b4976b6dfae6bc02e298f4 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17389 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-18intel/sandybridge: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I5b218ce3046493b92952e47610c41b07efa4d1de Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18intel/sandybridge post-car: Redo MTRR settings and stack selectionKyösti Mälkki
Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Also fixes regression of slower S3 resume path after commit 9b99152 intel/sandybridge: Use common ACPI S3 recovery Skipping low memory backup and using stage cache for ramstage decreases time spent on S3 resume path by 50 ms on samsung/lumpy. Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15790 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-15northbridge/via/vx800: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/via/vx800. Change-Id: I14a2b4d847f8aeb327d90f385dea998779fae24f Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17316 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15northbridge/via/cx700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/via/cx700. Change-Id: I6e25f898ab55ee959f1b3b8aba9616c3ba18986d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17315 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15northbridge/intel/i855: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i855. Change-Id: Iae66d1ef838095a560868d9c9ff81f4208f814f1 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17314 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15northbridge/amd/agesa/family10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/agesa/family10. Change-Id: I5723e217fc739ab576cbe3a1ee6d92023190267c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17313 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 13:09:35 +0000