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2012-03-27Add the support for RDC R8610 NorthbridgeRudolf Marek
So far the it just setups the internal resource management for coreboot and detects the memory size. Change-Id: I8506390fa6656abfa40d92b8f6ede9b91fe98680 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/807 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16Fix AMD Fam15 CBMEM allocationStefan Reinauer
The Fam15 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: I8a00e05884bdb1d1a4a012433b0adfbb9eb22983 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/796 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16Fix AMD Fam12 CBMEM allocationStefan Reinauer
The Fam12 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: I1eca18e21fa59ae32e802d8452e42e8b7a3575cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/795 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16Fix AMD Fam10 CBMEM allocationStefan Reinauer
The Fam10 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: Id6c4128d8f5f6a417f83daa3a39b2bfc8e810f8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/794 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16AMD Agesa: delete no-op bootblock filesKyösti Mälkki
Removes files: src/northbridge/amd/agesa/family10/bootblock.c src/northbridge/amd/agesa/family12/bootblock.c src/northbridge/amd/agesa/family14/bootblock.c src/northbridge/amd/agesa/family15/bootblock.c Change-Id: Ic3617a673b38d065ca272c4de8ef765ecd3f98b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/793 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove the explicit selects from the mainboards. Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/792 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Agesa leaking KconfigKyösti Mälkki
Kconfig leaked XIP_ROM_SIZE to other platforms and also defined obsolete option XIP_ROM_BASE. Alias AMD_AGESA as NORTHBRIDGE_AMD_AGESA. Break the circular dependency with family15 Kconfig. Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/773 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build. Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time which model of I945 the driver is built for. Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16VIA southbridge K8T890: Apply un-written naming rulesKyösti Mälkki
Use separate Kconfig option to select a driver directory for build and the specific type of southbridge to support. Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Fam14 cbmen allocationMarc Jones
The Fam14 northbridge.c had hardcoded the cbmem size. It should use in cbmem.h instead. Change-Id: I910329fc98a4cf04dc81ef66f3aa05a1916f5b1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/790 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-03-15Clean up whitespace in fam14 northbridge.cMarc Jones
Change-Id: Id7947d7f3c67fdda67861065b1bc7a519b97208f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/789 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-02Fix ECC disable option for AMD Fam10 DDR2 and DDR3.Marc Jones
The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/670 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17Avoid ../../.. paths in ASL filesPatrick Georgi
The current directory is always part of the search path of cpp when using #include "..." Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/648 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17Rename i945 ACPI files to not carry an i945_ prefixPatrick Georgi
In the spirit of the earlier renames. Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/647 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17Remove whitespace.Patrick Georgi
Fix issues reported by new lint test. Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-16AGESA F15: AGESA family15 model 00-0fh northbridge wrapperKerry Sheh
Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/556 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16RD890: AMD RD890/SR56X0 CIMX wrapperKerry Sheh
Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/559 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-10Remove non-existent includeSven Schnelle
Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/619 Tested-by: build bot (Jenkins)
2012-02-10i5000: halt second BSPSven Schnelle
If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/615 Tested-by: build bot (Jenkins)
2012-02-02Add Intel i5000 Memory Controller HubSven Schnelle
Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/491 Tested-by: build bot (Jenkins)
2012-01-31northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig optionPeter Stuge
Originally brought up by Sven Schnelle in March 2011 http://patchwork.coreboot.org/patch/2801/ http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html On some mainboards it may be neccessary to reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other mainboards, such as Lenovo X60 and T60, the check always creates false positives, effectively making it impossible to resume. The SLFRCS register is documented on page 197 of Mobile Intel® 945 Express Chipset Family Datasheet Document Number: 309219-006 which is publically available, and the register indicates if a memory channel is guaranteed to be in self-refresh mode (if bit = 1), or that a memory channel *may or may not be* in self-refresh mode (if bit = 0). The register can thus only be used to positively learn that memory is in self-refresh. It is not known for sure that memory is *not* in self-refresh. The register is reset by the PWROK signal, which *should* go low during S3, and go high again when resuming, so it is unsurprising that SLFRCS has already been cleared when we read the register. Sven's measurements of the CKE signal on a ThinkPad shows that memory remains in self-refresh indefinitely, until coreboot re-initializes the memory controller, even when SLFRCS bits were = 0. Boards which require a warm reset when SLFRCS bits are cleared must now explicitly enable the check in the mainboard Kconfig file. This commit selects the new option in all existing i945 mainboards. A follow-up commit will remove the option for ThinkPads. Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/590 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-01-26Make Geode GX2 VGA setup work.Nils Jacobs
Add MSR register write for VGA memory setup Add missing license Add bit explanation Change-Id: I1cb36eeccd84f0056c829f50d9864047654ce906 Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/580 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-10i945: fix tsc udelay()Sven Schnelle
The comparision is the wrong way round: as long as tsc is below tsc1, the timeout is not reached Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/530 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-07Update geode GX2 tree to match LX.Nils Jacobs
Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/512 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-05Clean up AMD Fam14 SSDTMarc Jones
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This fixes some ACPI errors in Linux and Windows bluescreens. The Persimmon acpi_tables.c is where the main changes were made and then replicated in the other Fam14 boards. Please test the other mainbords if you have one. Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/516 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2011-12-31White space and coding style fixes.Nils Jacobs
Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736 Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/511 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-xFlorian Zumbiehl
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/481 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-02Change AMD vendorcode buildKyösti Mälkki
Apply the normal method of recursively including subdirectories for src/vendorcode. Remove redundant references under mainboard and northbridge. Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/468 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-23k8 raminit: fix bug, improve clock selection, add clock limit for sock754Florian Zumbiehl
in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/377 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-16fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminitFlorian Zumbiehl
Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/376 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-07Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26Florian Zumbiehl
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/370 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-31Add support for E7505 northbridge.Kyösti Mälkki
Adapted from northbridge/intel/e7501 with only minor changes. This commit provides minimal patch from e7501 and I prefer any cosmetic clean-up to be done after initial merge. Due the incomplete register specifications, it is safer to have e7505 as a separate directory in case I improve it to support wider range of memory configurations. I have no e7501 to test with. Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/295 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Clear improper use of CONFIG_CACHE_AS_RAMKyösti Mälkki
Choice between printk/print_ is related to CAR, but really depends whether we compiled with GCC or ROMCC. Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/347 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28copy e7501 component to e7505Stefan Reinauer
Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/310 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-19I945: replace #if defined() by #ifSven Schnelle
config.h defines also unset config options (as "0") so #ifdef matches both settings, which isn't what we want. Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/293 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/266 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15use acpi.h include instead of manually adding acpi_slp_type.Stefan Reinauer
Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/276 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix compilation of AMD GX2 northbridge code with gcc 4.6Stefan Reinauer
Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/267 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix compilation of VIA CN700 northbridge code with gcc 4.6Stefan Reinauer
Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14fix compilation of intel/sch northbridge code with gcc 4.6Stefan Reinauer
Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-12amdk8: ASL include for K8 temperature sensor support in ACPIChristoph Grenz
Add a ACPI Source Language snippet which if included as shown in the comments in the file, exposes the 4 possible temperature sensors in the CPU as ACPI thermal zones. Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/222 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platformsenok71
The hp/dl145_g1 motherboard did not work since commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit added TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process stopped very early (no console output whatsoever). The same symptom was reported on other AMDK8 based boards with amd8111 southbridge chips. This commit seems to fix the bug. It adds a bootblock.c under src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the problem was that enum_ht_chains needs to be called before the southbridge bootblock.c function, not after. Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/235 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-24Add AMD Family 10h PH-E0 supportQingPei Wang
the patch file comes from src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE /F10MicrocodePatch010000bf.c Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802 Signed-off-by: QingPei Wang <wangqingpei@gmail.com> Reviewed-on: http://review.coreboot.org/202 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-14AMD F14 Northbridge updatesefdesign98
This change is warning and whitespace fixes in the northbridge code for AMD Family 14 rev C0 cpu update. This does not address warnings in the mainboard, Agesa, Cimx, or southbridge code. Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/134 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-09Replace while with do; while to avoid repetitionNoe Rubinstein
Cosmetic only; replaces some 'while' loops with 'do; while' loops to avoid repetition. Replacement performed by the Ruby expression: t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/, "\\1do \\2\n\\1\\3;") Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/183 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09Report GSE chipset and warn if the code has been compiled for the wrong chipset.Stefan Reinauer
It would be nicer to unify the code so that it does all detection at runtime instead of compile time (but that would also significantly increase code size) so if someone else wants to give it a shot... Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/184 Tested-by: build bot (Jenkins)
2011-09-07AMD F14 southbridge updateKerry She
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04northbridge/intel/i440bx: Registered SDRAM modules support and fixesKeith Hui
Adds support for initializing registered SDRAM modules on Intel 440BX northbridge. Drops unneeded romcc-inspired programming tricks. Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC module has been detected in a row via SPD; also drops an unneeded intermediate variable used in setting them. Boot tested on ASUS P2B-LS with regular and registered ECC SDRAM under Linux and memtest86+. Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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