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2004-11-10- Remove e7501 root_complexEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10adl855pc supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05CONFIG_CHIP_NAME to control config chip.h without .nameYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- Add a new chip northbridge/amd/amdk8/root_complexEric Biederman
- Moving the functionality around in northbridge/amd/amdk8/northbridge.c to put the pci_domain and the apic bus on the root_complex. Everything else remains with the individual northbridges. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-03*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02get qemu-i386 target building againStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30- To reduce confuse rename the parts of linuxbios bios that run fromEric Biederman
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload... - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86 - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB. - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work. - Start using romcc's built in preprocessor (This will simplify header compiler checks) - Add helper functions for examining all of the resources - Remove debug strings from chip.h - Add llshell to src/arch/i386/llshell (Sometime later I can try it...) - Add the ability to catch exceptions on x86 - Add gdb_stub support to x86 - Removed old cpu options - Added an option so we can detect movnti support - Remove some duplicate definitions from pci_ids.h - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic - Minor romcc bug fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-29Changes to allow Via/Epia code to be compiled after recent code changes.Mark Wilkinson
New Files :- src/cpu/via/model_centaur/Config.lb src/cpu/via/model_centaur/model_centaur_init.c Updated Files :- src/arch/i386/include/arch/smp/mpspec.h - make write_smp_table a define for non smp systems src/cpu/x86/lapic/lapic_cpu_init.c - change possible typo src/mainboard/via/epia/Config.lb src/mainboard/via/epia/Options.lb src/mainboard/via/epia/auto.c src/mainboard/via/epia/chip.h src/mainboard/via/epia/failover.c - updated after recent code changes src/northbridge/via/vt8601/chip.h src/northbridge/via/vt8601/northbridge.c src/northbridge/via/vt8601/raminit.c - corrections after recent code changes to allow compiling src/southbridge/via/vt8231/chip.h src/southbridge/via/vt8231/vt8231.c - initial pass to allow compiling after recent code changes. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27- Look for all 8 possible cpusEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27sizeram removal/conversion.Eric Biederman
- mem.h and sizeram.h and all includes killed because the are no longer needed. - linuxbios_table.c updated to directly look at the device tree for occupied memory areas. - first very incomplete stab a converting the ppc code to work with the dynamic device tree - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources). - First stab at Pentium-M support - add part/init_timer.h making init_timer conditional until there is a better way of handling it. - Converted all of the x86 sizeram to northbridge set_resources functions. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27- kill the broken and duplicate 855pm directory. Hopefully I have keptEric Biederman
the least broken one. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25ops and tscYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25s2735 minor changesYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23- For now use port 0x80 based delays in for the e7501 memory initialization.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23- Update e7501 northbridge.c to work in the new structure.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22- kill typo so resources are not mixed up in amdk8/northbridge.cEric Biederman
- Enable resources on the lpc bus. PCI now longer do this by default for their children unless they are bridges. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-20Tyan update to work with new CPU ConfigYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19- Fix typo with reversing memory resources.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- HDAMA boots!Eric Biederman
- Set the bootstrap processor flag in the mptable. - Implement 64bit support in our print statements - Fix the reporting of how many cpus we are waiting to stop. It is the 1 less than the actual number of cpus running. - Actually enable cpu_initialization. - Fix firstsiblingdevice in config.g - Add IORESOURCE_FIXED to all of the resources set by config.g - Fix the apic_cluster rule to add an apic_cluster path not an apic path. - Add a div64.h to assist in the 64bit printf. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- Sync up northbridge/amd/amdk8Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- Update the header files in reset_test.cEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- First pass through with with device tree enhancement merge. Most of the ↵Eric Biederman
mechanisms should be in place but don't expect anything to quite work yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06epia-m supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06f'ing thing still won't work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30mods for i855pm that don't seem too wrong. ha!Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-28add support for ICH4. more i955pm stuff.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-30more fixes.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-26just a few changes before we hit the big fun.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-25more updates for 855Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24stupid ron! need to start names with a letter.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-23random fixes.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-23dpx114Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-23adding 855pmRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-08move default_resource_map to its own fileLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-06fixed again.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-06fix for simple errorRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-01Intel E7501 P64H2 ICH5R supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-28add northbridge code for qemu-i386Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-05Add extra phase before memory init.Greg Watson
Rename sdram_init to memory_init NOTE: need to test sandpoint and ep boards! git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-05memory and pci up!Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03first cutGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03prelim sdramGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03Make names more sensible.Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-24added AGP support for AMD K8Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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