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2017-05-04nb/intel/x4x/raminit: Change reset type on incomplete raminit resetArthur Heymans
The checkreset() function checks if raminit previously succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the system BOOT_PATH_RESET path will be taken. This boot path can only successfully initialize memory if the system was reset from a state where raminit succeeded, which is not the case here. This can be fixed by issuing a cold reset instead of a hot reset. Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03nb/intel/gm45: Set display backlight according to EDID stringArthur Heymans
Add some known good values for some thinkpads displays. Known good means that at this pwm frequency the display is evenly lit on all duty cycles, the display makes minimal to no noise at lower duty cycles and the display does not flicker. This values differs from vendor (which uses an obviously wrong display clock (190MHz instead of 320MHz) resulting in frequency more than 60% off the intended value. TESTED on Thinkpad X200 with edid ascii string in list and removed from list to see if notice message is shown. Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03nb/intel/gm45/gma.c: Decode EDID before NGI pathArthur Heymans
This allows to use EDID data outside of NGI path without needing to fetch it twice. Change-Id: I6a540b1d036a9f38b44fd004309601630861f6e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-02amd/pi/00670F00: Reserve A0000-FFFFFMarshall Dawson
Claim memory-mapped regions in the legacy area. Claim an MMIO resource for the A000 and B000 segments, and reserved resource for C000 through F000 segments. These changes allow code and information to be retained in the event unused regions get wiped. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit d612d4fe69881609d42053496409c452e1014947) Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19156 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-05-01nb/intel/sandybridge/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: I97c3402ac055991350732e55b0dda042b426c080 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01nb/intel/nehalem/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01nb/intel/fsp_sandybridge/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19307 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28nb/amdk8: Link coherent_ht.cArthur Heymans
Change-Id: I1ef1323dc1f3005ed194ad82b75c87ef41864217 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19367 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-28nb/amd/amdk8: Link reset_test.cArthur Heymans
This needs some extra headers in amdk8/raminit.c that were otherwise provided by that file. Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19360 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-27cpu/amd/pi: Change wrapper to use config optionMarshall Dawson
Add a check for vboot when locating the binaryPI image. There is currently an ordering problem using cbmem to locate the image when vboot is present. Vboot inserts its locator into the search process so that memory can be checked before flash is queried. For the earliest calls using the wrapper, DRAM has not been set up and cbmem not initialized in romstage. This change prevents an endless loop when vboot searches cbmem. This change has another side effect. When vboot is in effect, the change forces the RO binaryPI to be used even when on either of the RW paths. There is currently no ability to relocate the XIP image for use in a RW region. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474) Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27nb/amd/amdk8: Link raminit_f.cArthur Heymans
For this debug.c needs to be linked too. Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19030 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-26nb/pineview/raminit: Don't do Jedec init on resume from S3Arthur Heymans
This is not needed. Change-Id: Id19a00c1546b7a71d90aa8c7e43e6efde1e9fbbc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19425 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-24nb/intel/pineview: Select RELOCATABLE_RAMSTAGEArthur Heymans
Change-Id: Id1b7b98b4fba745ac0d55638b6a5cceba3c329ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19415 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-24nb/intel/pineview: Move to early cbmemArthur Heymans
TESTED on D510MO. Change-Id: I05aa40df0d2a090fcf734416669e9e1bbff094e4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19414 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-24nb/pineview/raminit: Fix raminit failing on hot reset pathArthur Heymans
For raminit to succeed on a hot reset the following things are prevented from running: * Clearing self refresh * Setting memory frequency * programming sdram dll timings * programming rcomp TESTED on Intel d510mo. Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19337 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-24northbridge/haswell: clean up native graphics init codeMatt DeVillier
Clean up NGI code now that libgfxinit has replaced old C code: - replace #if preprocessor guards with if (IS_ENABLED(...)) - don't guard variable declarations - remove code that would only be executed for old NGI / isn't used by libgfxinit Test: boot google/wolf with VBIOS, NGI, and UEFI/GOP video init, observe payload and pre-OS graphics display functional. Change-Id: I96e74f49ea70e09cbac6f8af561de3e18fa7d260 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19327 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-22nb/intel/pineview/raminit: Fix CONFIG_DEBUG_RAM_SETUP=y not compilingArthur Heymans
The function decode_spd uses undeclared variables and an incorrectly initialized array. Change-Id: Ib45a8b2946c04c270e29524675b1f09d491d282b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19336 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-19console: Add convenient debug level macros for raminitNico Huber
Change-Id: Ib92550fe755293ce8c65edf59242a2b04327128e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19332 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-19nb/intel/gm45: Hide some output behind DEBUG_RAM_SETUPNico Huber
Hide some (partial) lines behind DEBUG_RAM_SETUP and shorten some messages. This saves some KiB to make CBMEM console more usable in romstage. Change-Id: I62a84ca662ee778b7c1deb71247f3b01a37858fa Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-17[nb|sb]/amd/[amdfam10|sb700]: Add LPC bridge ACPI names for NB/SBTimothy Pearson
Adds the necessary plumbing for acpi_device_path() to find the LPC bridge on the AMD Family10h/15h northbridges and SB700 southbridge. This is necessary for TPM support since the acpi path to the LPC bridge doesn't match the built-in default in tpm.c This is a port of GIT hash d8a2c1fb by Tobias Diedrich. BUG=https://ticket.coreboot.org/issues/102 Change-Id: I1c514e335e194b2864599e5419cfaee830b94e38 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19282 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17nb/amd/amdk8/exit_from_self.c: Use linker instead of includeArthur Heymans
Don't #include *. but use linker. Change-Id: I716b37e71ab3a4409709357f50f79e3149ede2b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-15nb/intel/x4x/Kconfig: Don't fix CBFS_SIZE on i82801gx southbridgeArthur Heymans
The x4x northbridge can be paired with either an ICH7 (in the case of g41) or an ICH10 (all other cases: g45, q45, p45, ...). Only ICH10 sometimes occurs with a descriptor, gbe and an ME region. ICH7 is always descriptorless so it makes no sense to fix CBFS to accommodate for those other objects. Change-Id: I4a01dfdbce1807e44932a3ac812110382332abd8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19181 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-15AGESA: Change guard for VBIOS calloutKyösti Mälkki
Change-Id: Ie046fd3c413585131669193a6669358adf709028 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19268 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-14northbridge/via/cn700/acpi: Add the host bridgeLubomir Rintel
Includes the DRAM controller device that knows which where the division between addresses routed to the main memory and to the PCI bus is. Change-Id: Id4cfeb8ff32de37723eee68a61c576e657dad30b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14northbridge/via/cn700: Add a default VGA BIOS idLubomir Rintel
This is the actual PCI Id of the internal graphics. Change-Id: I2a25ed35a5b01de6da905619fa9fce96738d1c0e Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18895 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-14northbridge/via/cn700: Add IORESOURCE_BRIDGE resources to AGP bridgeLubomir Rintel
Without them the BS_DEV_RESOURCES stage won't traverse the bridge and the graphics controller would be left without resources assigned. Even worse, the resources would stay based in offset 0 which confuses the MTRR setting code and causes a good chunk of the DRAM to be set to type write combining. With the patch applied, the resources are set: Show resources in subtree (Root Device)...After assigning values. ... PCI: 00:01.0 child on link 0 PCI: 01:00.0 + PCI: 00:01.0 resource base ffff size 0 align 0 gran 0 limit ffff flags 60080100 index 0 + PCI: 00:01.0 resource base f8000000 size 4000000 align 26 gran 0 limit fbffffff flags 60081200 index 1 + PCI: 00:01.0 resource base fc000000 size 1010000 align 24 gran 0 limit fd00ffff flags 60080200 index 2 PCI: 01:00.0 - PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 - PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 - PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 + PCI: 01:00.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10 + PCI: 01:00.0 resource base fc000000 size 1000000 align 24 gran 24 limit fcffffff flags 60000200 index 14 + PCI: 01:00.0 resource base fd000000 size 10000 align 16 gran 16 limit fd00ffff flags 60002200 index 30 And the caching mode is set properly: MTRR: Physical address space: -0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 1 -0x0000000004000000 - 0x000000000e000000 size 0x0a000000 type 6 -0x000000000e000000 - 0x0000000100000000 size 0xf2000000 type 0 +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x000000000e000000 size 0x0df40000 type 6 +0x000000000e000000 - 0x00000000f8000000 size 0xea000000 type 0 +0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1 +0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0 The problem was also spot and discussed here: http://coreboot.coreboot.narkive.com/E9eGauzH/via-c7-on-bcom-winnet-p680-l1-l2-cache-very-slow Change-Id: Idb4979b206838dd6455b2a16de14dc74f83af921 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18894 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14northbridge/via/cn700: Add some delays during raminitLubomir Rintel
Otherwise, it locks up quickly. Not sure which ones are actually needed and why, couldn't bisect it into removing even a single one. The factory BIOS on a Neoware G170 does 200 0xed reads between setting the registers too. Change-Id: I6aa38768d84dd42c9c720c917a99e6b4b1e03427 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18893 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14nb/intel/i945: Fix PEG port on 945gcArthur Heymans
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203). Not running PCIEx16 init which is valid for 945gm seems to fix all issues and instabilities related to the PEG port. According to lspci the link width is at the desired x16. It is unknown if devices requesting a lower width work automatically or need more configuration. What happens is that IGD gets disabled by the disable function in gma.c when an external GPU is found unless CONFIG_ONBOARD_VGA_IS_PRIMARY is set. Setting IGD as secondary makes Linux (4.10) hang, so this behavior is a requirement for now. TESTED on P5GC-MX with a discrete GPU and both CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset. Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18549 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-10nb/amdk8/(pre_)f.h: Don't declare global variable in headerArthur Heymans
This is needed if one wants to use the header more than once. Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19029 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-08AGESA: Add helpers to track heap relocationKyösti Mälkki
Change-Id: Ib43e59e4d4ee5e48abf7177b36cb06fdae40bde9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-07nb/intel/i945: Move INTEL_EDIDPatrick Rudolph
All boards select INTEL_EDID, move it to nb folder. Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19086 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-07nb/intel/sandybridge/raminit: Fix odt stretchPatrick Rudolph
Move odt stretch into own function. Apply workaround on SandyBridge C-stepping CPU only. Apply odt stretch on all other CPU types. Don't depend on empty DIMM detection, as in case one slot is empty ref_card_offset is zero. Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17616 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-07nb/intel/sandybridge/raminit: Always run quick_ram_checkPatrick Rudolph
quick_ram_check doesn't change contents of memory. Run it in S3 resume, too. Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17615 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-07nb/intel/sandybridge/raminit: Reduce log levelPatrick Rudolph
Silency noisy raminit logging by: * Removing verbose logging from loops. * Printing detailed summary at end of loop instead. * Using the same scheme already present in some functions. Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17611 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-07nb/intel/sandybridge/raminit: Fix normalize_trainingPatrick Rudolph
Remove cross rank/cross channel dependency. I guess this is a mistake that could lead to instabilities. Tested on Lenovo T430 (Intel IvyBridge). Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17610 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins)
2017-04-06northbridge/via/cn700: Get rid of #include raminit.cLubomir Rintel
Using linker instead of '#include *.c'. Change-Id: Ie1bc538aa29c4f18dd6f31a83d3da58f196f2078 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/19081 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-05AGESA: Disable CAR with empty stackKyösti Mälkki
Calling disable_cache_as_ram() with valuables in stack is not a stable solution, as per documentation AMD_DISABLE_STACK should destroy stack in cache. Change-Id: I986bb7a88f53f7f7a0b05d4edcd5020f5dbeb4b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18626 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05AGESA: Move romstage main entry under cpuKyösti Mälkki
As we now apply asmlinkage attributes to romstage_main() entry, also x86_64 passes parameters on the stack. Change-Id: If9938dbbe9a164c9c1029431499b51ffccb459c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18624 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-04nb/intel/sandybridge/raminit: Add default valuesPatrick Rudolph
Add 100 Mhz reflock default values for Ivybridge. Some values are extracted from MRC, those marked as guessed needs to be verified. Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800. Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17609 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-04nb/intel/sandybridge/raminit: Add debugging outputPatrick Rudolph
Add debugging output to normalize_training. Tested on Lenovo T420. Change-Id: I1d787f7ead6cf35ee142a8848837840c91cb6967 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17608 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2017-04-04nb/intel/sandybridge/raminit: Add 100MHz refclock supportPatrick Rudolph
Add support for 100MHz reference clock on ivybridge. Allows to use more frequencies than sandybridge. Tested on Lenovo T430 (Intel IvyBridge) on DDR3-1800. Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17607 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-04nb/intel/sandybridge/raminit: Use Ivy Bridge specific valuesPatrick Rudolph
Use Ivy Bridge specific magic values on Ivy Bridge instead of Sandy Bridge values. The values are extracted from MRC.bin. Should increase raminit stability. Tested on Lenovo T430 (Intel IvyBridge). Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17606 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-04AGESA: Refactor S3 support functionsKyösti Mälkki
Producer and consumer of these buffers now appear in same file. Also add test for uninitialized NonVolatileStorage in SPI. Change-Id: Ibbf6581a0bf1d4bffda870fc055721627b538b92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19037 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-03AGESA: Simplify parameters for S3 support functionsKyösti Mälkki
This save/restore facility operates on the same datablock. Change-Id: I6e1f176adc2addbf2659c724f94c1b8d46d4838f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19026 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-03AGESA: Move guard on S3 support functionsKyösti Mälkki
Only guard the parts that are problematic for romstage. Also intention is to move AMD_S3LATE_RESTORE to ramstage in followup work, it will need OemS3LateRestore. Change-Id: Ie9c1fb3f3f0ab1951771ed829d4acdd8a59d8fbf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19025 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-03AGESA: Move EmptyHeap() callKyösti Mälkki
Specification says to do CAR teardown as part of AmdInitPost(). Move initializing the final AGESA heap storage to AmdInitEnv() so the buffer is not invalidated without writeback. Change-Id: I3a5d497d0e25ec291f722e9f089bc8928238c3f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19024 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-03nb/intel: Deduplicate vbt headerPatrick Rudolph
Move header and delete duplicates. Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18903 Tested-by: build bot (Jenkins) Tested-by: coreboot org <coreboot.org@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner
Some Chrome OS boards previously didn't have a hardcoded vboot configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE, etc.) selected from their SoC and mainboard Kconfig files, and instead relied on the Chrome OS build system to pass in those options separately. Since there is usually only one "best" vboot configuration for a certain board and there is often board or SoC code specifically written with that configuration in mind (e.g. memlayout), these options should not be adjustable in menuconfig and instead always get selected by board and SoC Makefiles (as opposed to some external build system). (Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for Pistachio/MIPS was never finished. Trying to enable even post-romstage vboot leads to weird compiler errors that I don't want to track down now. Let's stop pretending this board has working Chrome OS support because it never did.) Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28AGESA: Introduce AGESA_LEGACY and its counterpartKyösti Mälkki
We define AGESA_LEGACY as an implementation of mainboard that has its romstage main completely under mainboard/ directory. We have learnt from other platforms this approach has several downsides when it comes to making platform-wide improvements. We start by creating per-family romstage.c file, which boards will gradually take into use by removing the AGESA_LEGACY Kconfig option we here apply to all of them. Change-Id: Id01931e185a023039a60af16a678de9966db8d65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18619 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
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