coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-01-18	security/intel/stm/StmPlatformSmm.c: Remove repeated word	Elyes HAOUAS
2021-01-15	build system: Always add coreboot.pre dependency to intermediates	Patrick Georgi
2021-01-14	build system: Structure and serialize INTERMEDIATE	Patrick Georgi
2021-01-08	*/Makefile.inc: Add some INTERMEDIATE targets to .PHONY	Arthur Heymans
2021-01-07	security/intel/txt: Don't run SCHECK on CBnT	Arthur Heymans
2021-01-04	security/intel/txt/ramstage.c: Fix clearing secrets on CBNT	Arthur Heymans
2020-12-29	sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurable	Arthur Heymans
2020-12-02	cbfs: Simplify load/map API names, remove type arguments	Julius Werner
2020-11-10	sec/intel/cbnt: Stitch in ACMs in the coreboot image	Arthur Heymans
2020-11-04	haswell: Add Intel TXT support in romstage	Angel Pons
2020-11-04	sec/intel/txt: Add support for running SCLEAN in romstage	Angel Pons
2020-10-28	sec/intel/txt/Kconfig: Remove the menu for including ACMs	Arthur Heymans
2020-10-28	sec/intel/txt/Makefile.inc: Include ACMs using Kconfig variables	Arthur Heymans
2020-10-22	sec/intel/txt: Split MTRR setup ASM code into a macro	Angel Pons
2020-10-22	sec/intel/txt: Add `enable_getsec_or_reset` function	Angel Pons
2020-10-22	sec/intel/txt: Extract BIOS ACM loading into a function	Angel Pons
2020-10-22	sec/intel/txt: Only run LockConfig for LT-SX	Angel Pons
2020-10-22	sec/intel/txt: Always run SCHECK on regular boots	Angel Pons
2020-10-22	sec/intel/txt: Allow skipping ACM NOP function	Angel Pons
2020-10-22	sec/intel/txt/ramstage.c: Do not init the heap on S3 resume	Angel Pons
2020-10-22	sec/intel/txt/ramstage.c: Extract heap init into a function	Angel Pons
2020-10-22	sec/intel/txt: Add and fill in BIOS Specification info	Angel Pons
2020-10-22	sec/intel/txt/common.c: Only log ACM error on failure	Angel Pons
2020-10-22	sec/intel/txt: Move DPR size to Kconfig	Angel Pons
2020-10-17	intel/txt: Add `txt_get_chipset_dpr` function	Angel Pons
2020-10-17	security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]	Angel Pons
2020-10-17	sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACM	Angel Pons
2020-10-15	sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPE	Arthur Heymans
2020-10-15	security/intel/txt: Use `smm_region()` to get TSEG base	Angel Pons
2020-10-12	security/intel/txt: Add and use DPR register layout	Angel Pons
2020-10-12	security/intel/txt: Clean up includes	Angel Pons
2020-10-12	security/intel/stm: Add options for STM build	Eugene Myers
2020-10-08	security/intel/txt: Print chipset as hex value	Christian Walter
2020-10-01	security/intel/stm: Fix size_t printf format error	Felix Held
2020-09-30	security/intel/stm: Fix size_t printf format error	Eugene D Myers
2020-09-21	src/security: Drop unneeded empty lines	Elyes HAOUAS
2020-08-30	security/intel/txt/getsec.c: Do not check lock bit	Angel Pons
2020-08-30	security/intel/txt: Add missing definitions	Angel Pons
2020-08-18	src: Remove unused 'include <lib.h>'	Elyes HAOUAS
2020-08-07	security/intel/txt: Fix variable MTRR handling	Angel Pons
2020-08-07	security/intel/txt: Allow using CF9 reset, too	Angel Pons
2020-08-06	security/intel/txt: Avoid shifting by a negative value	John Zhao
2020-07-31	security/intel/txt: Add Intel TXT support	Philipp Deppenwiese
2020-07-21	security/intel/stm: Add missing <stdbool.h>	Angel Pons
2020-07-14	src: Remove unused 'include <cpu/x86/msr.h>'	Elyes HAOUAS
2020-05-18	src: Remove unused 'include <lib.h>'	Elyes HAOUAS
2020-05-13	src: Remove unused '#include <stddef.h>'	Elyes HAOUAS
2020-05-11	treewide: Convert more license headers to SPDX style	Patrick Georgi
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-08	{security,soc}/*/Kconfig: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS