Age | Commit message (Collapse) | Author |
|
Cezanne must use cold resets. Change the warm reset request to always
set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power
cycles, set it early for good measure.
BUG=b:184281092
TEST=Majolica successfully resets using 0xcf9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|