coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-02-11	soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler	Felix Held
2021-02-11	soc/amd: include cpu/x86/smm directory in common SMM Makefile	Felix Held
2021-02-11	soc/amd: move southbridge_smi_handler to common code	Felix Held
2021-02-11	soc/amd: factor out common SMM relocation code	Felix Held
2021-02-11	soc/amd/cezanne: add empty SMM-handler	Felix Held
2021-02-10	soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports	Felix Held
2021-02-10	soc/amd/cezanne: Add verstage support	Raul E Rangel
2021-02-10	soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI	Raul E Rangel
2021-02-10	soc/amd/cezanne: Add SPI registers	Raul E Rangel
2021-02-10	soc/amd/cezanne/chip: add empty set_mmio_dev_ops	Felix Held
2021-02-10	soc/amd/cezanne/chip: add empty cpu_bus_ops	Felix Held
2021-02-10	soc/amd: Move soc_route_sci to common/blocks/smi/smi_util	Felix Held
2021-02-09	soc/amd/cezanne: Add root_complex	Raul E Rangel
2021-02-09	soc/amd/cezanne: add empty CPU driver	Felix Held
2021-02-09	soc/amd/cezanne: Enable early LPC support in bootblock stage	Zheng Bao
2021-02-09	soc/amd,intel: Drop s3_resume parameter on FSP-S functions	Kyösti Mälkki
2021-02-07	soc/amd/cezanne/romstage: Store early dram region	Raul E Rangel
2021-02-07	soc/amd/cezanne/Makefile.inc: Fix indentation	Raul E Rangel
2021-02-07	soc/amd/cezanne/pcie_gpp: scan internal PCI buses	Felix Held
2021-02-07	soc/amd/cezanne/chip: add PCI bus scanning	Felix Held
2021-02-05	soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges	Felix Held
2021-02-05	soc/amd/cezanne/fch: add ACPI I/O port setup	Felix Held
2021-02-05	soc/amd/cezanne: populate some FSP-M UPDs	Felix Held
2021-02-03	soc/amd/cezanne: remove UART2/3 AOAC device offsets	Felix Held
2021-02-03	amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)	Zheng Bao
2021-01-31	soc/amd/cezanne/Kconfig: select common PSP gen2 support	Felix Held
2021-01-31	soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 stepping	Felix Held
2021-01-30	soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls	Felix Held
2021-01-29	soc/amd/cezanne: add empty ramstage FCH support	Felix Held
2021-01-29	soc/amd/cezanne/chip: add FSP silicon init driver call	Felix Held
2021-01-29	device/Kconfig: Declare MMCONF symbols' type once	Angel Pons
2021-01-28	soc/amd/cezanne/Kconfig: move selections in alphabetical order	Felix Held
2021-01-28	soc/amd/cezanne/chip: add empty SoC device operations	Felix Held
2021-01-28	soc/amd/cezanne: compress FSP binaries in CBFS	Felix Held
2021-01-27	soc/amd/cezanne: Add UCODE firmware to CBFS	Zheng Bao
2021-01-27	soc/amd: Throw an error if FWM_POSITION_INDEX is empty	Zheng Bao
2021-01-24	soc/amd/cezanne/Kconfig: select missing SSE2 option	Felix Held
2021-01-24	soc/amd/cezanne/Kconfig: select X86_AMD_FIXED_MTRRS	Felix Held
2021-01-24	soc/amd/cezanne: add basic romstage	Felix Held
2021-01-24	soc,vendorcode/amd/cezanne: add basic FSP integration	Felix Held
2021-01-24	soc/amd/cezanne: Add PSP integration for cezanne	Zheng Bao
2021-01-22	soc/amd/cezanne: add pci_devs.h	Felix Held
2021-01-21	soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16	Felix Held
2021-01-20	soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGE	Felix Held
2021-01-18	ACPI: Select ACPI_SOC_NVS only where suitable	Kyösti Mälkki
2021-01-15	soc/amd/cezanne,picasso/uart: remove unneeded struct name	Felix Held
2021-01-14	soc/amd/cezanne: add remaining non-ACPI parts of UART support	Felix Held
2021-01-14	soc/amd/cezanne: add AOAC support	Felix Held
2021-01-14	soc/amd/cezanne: add console UART support	Felix Held
2021-01-11	soc/amd/cezzane: Add a minimal chipset tree	Furquan Shaikh