Age | Commit message (Collapse) | Author |
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If one wishes to use the functions guarded here, he
has to have datasheet open anyways. It should be clear
from there which regions are supported and which are not.
TEST=Reproducible build of google/aleena.
Change-Id: I0c1f0c9c9a6711532c5078c08cdf9e6612f3bc9c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Builds that would otherwise be reproducible are sometimes
broken due to added #include combined with __LINE__ used
in assert() statement.
Change-Id: If4a02393799a34bbae4f6e506052774526c1a969
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37266
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The standard PCI register space for D14F0 is accessible at 0xfed80000.
Add functions for use as helpers.
Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The LPC-ISA bridge supports two ranges for SuperIO control registers.
Add a generic function to allow a mainboard to enable the appropriate
range. Provide #define values that are more descriptive than the
register's field names.
Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35271
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All solid state devices have vendor id defined by JEDEC specification JEP106,
which originally allocated only 7 bits for it plus parity. When number of
vendors exploded beyond 126, a banking proposition came maintaining
compatibility with older vendors while allowing for 4 extra bits (16 banks)
through the introduction of the concept "Continuation code", denoted by the
byte value of 0x7f.
Examples:
0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o
0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2
BUG=b:141535133
TEST=Build and boot grunt.
Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Use the new SPI code from common folder, delete spi.c. SPI related macros
must be single defined, in southbridge.h if they are used by files other
than the common SPI code, fch_spi.h if they are only used by the common
SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h,
because it can change between SOC.
BUG=b:136595978
TEST=Build and boot grunt using new SPI code, with debug enabled. Check
output.
Change-Id: I639973d993316a10daa7564462e689b2c183f536
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Create a new SPI code that overrides flash operations and uses the SPI
controller within the FCH to its fullest.
Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public)
BUG=b:136595978
TEST=Build and boot grunt using this code, with debug enabled. Check
output.
Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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It is already trivial to set D14F3x44 to 0, but add a function to wipe
both that and the settings in D14F3x48, along with x48's associated
addresses.
Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Include the file containing the typedefs for uint_*.
Change-Id: If33765b6dc4236c4b38860bfc4f2cef9b226b81d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Include the file containing the typedefs for uint_*.
Change-Id: I3eae80a677e9d6932dc115523da2c0819a371fa7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35268
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Include the file containing the typedefs for uint_*.
Change-Id: Ib0eea9bfd0c8d9e3eba257b561980accf5b4bab4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35267
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make the prototypes match what drivers/amd/agesa would
rather see, in preparation to use the same code with
open-source AGESA.
Change-Id: I1506ee2f7ecf3cb6ec4cce37a030c05f78ec6d59
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: If24bed8b3f10d945b9988445025409c8420dd07a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The decision to leave the alignment in stoneyridge was driven because
of a spec difference with picasso. AMD has checked the design
materials and has confirmed there was no change.
TEST=Build Grunt successfully
BUG=b:130343127
Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a method for the soc/amd/<product> to indicate what AcpiMmio
ranges are supported. Induce a build error if soc or mainboard
code is added which attempts to use an unsupported block.
This patch attempts to dissuade accessing unsupported blocks without
requiring the complexity of structures or reinitializing at the
beginning of a new stage.
TEST=boot grunt, force build errors by removing blocks in iomap.h
BUG=b:131682806
Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Document the AcpiMmio individual blocks better. This is in response
to a request in gerrit for
69486cac7: Create AcpiMmio functionality from stoneyridge
Correct comments that were inadvertently left in place from older
patches.
Change-Id: I4c16a866de5622e8cfbd3a08816b9d3182950d0e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32931
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change all arguments named "offset" to "reg" to match the others.
These should have gone into change
69486cac7: Create AcpiMmio functionality from stoneyridge
Change-Id: Ifdd00d0a5d1e03bfa68a13eeece2d2cfd56aa39d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32930
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reorder the biosram prototypes to match the rest of the file. Remove
prototypes for asf 32-bit functions that have not been implemented.
Change-Id: Ic2663158d8a71952c26eb37f34342a6ea5e58a42
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32929
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocate the alink access functions out of stoneyridge where they
were dead code. This source maintains the ability to access all
register spaces, however more modern APUs define only ABCFG in
the BKDGs.
BUG=b:131682806
Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32663
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocate generic sata support from stoneyridge to common/block.
BUG=b:131682806
Change-Id: I4e9eddaa291e5e03f4f8d88826973c5b8ee9a1c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32661
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The AcpiMmio block allowing direct access to the ACPI registers
has remained consistent across AMD models. Move the support from
soc//stoneyridge to soc//common.
BUG=b:131682806
Change-Id: I0e017a71f8efb4b614986cb327de398644599853
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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AMD devices traditionally have the LPC-ISA bus at 14.3 and the
definition has been very consistent. Relocate the feature from
stoneyridge into common/block.
BUG=b:131682806
Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The banked GPIO functionality in the AcpiMmio block has been consistent
since the Mullins product. Move the basic support into a common
directory.
Each product's pin availability, MUXes, and other details must remain
specific to the product.
The relocated source also drops the weak configure_gevent_smi() that
reports SMI is not available. The stoneyridge port relies on SMI
to do its initialization, similar to modern soc/intel devices. This
is the plan for future soc/amd ports, so make a missing function a
build error instead of a runtime warning.
BUG=b:131682806
Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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<types.h> is supposed to provide <stdint.h> and <stddef.h>.
When <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Move the stoneyridge AcpiMmio code into soc/amd/common.
The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000
commonly known as AcpiMmio. Implementations beginning with Mullins
enable decode in PMx04. Older designs use PMx24 and allow for
configuring the base address. Future work may support the older version.
Comparing the documentation for AMD's RRGs and BKDGs, it is evident that
the block locations have not been reassigned across products. In some
cases, address locations are deprecated and new ones consumed, e.g. the
early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks
are now at 0x1500, 0x1600, and 0x1700.
Note: Do not infer the definitions within the hardware blocks are
consistent across family/model products.
BUG=b:131682806
Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Each entrypoint to AGESA goes through the same sequence
and have same the function signature.
To avoid introducing bunch of preprocessor magic, rename
all the agesawrapper_amdXXX() functions that are actual
entrypoints to AGESA API, make them static, and provide
a single exposed entry function agesa_execute_state().
Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Third parameter ConfigPtr of the callout is of type
AP_EXE_PARAMS and needs to be passed back to AGESA
with AmdLateRunApTask() call.
Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27277
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There are several files under soc/amd that use units defined by file
porting.h. These units use upper case, and are not recognized by checkpatch,
thus causing problems when defining a pointer (request to use space before
and after the star symbol). These are the definitions from porting.h showing
the units that this patch will change and their coreboot definitions (not all
are actually used):
typedef uintptr_t UINTN;
typedef int64_t INT64;
typedef uint64_t UINT64;
typedef int32_t INT32;
typedef uint32_t UINT32;
typedef int16_t INT16;
typedef uint16_t UINT16;
typedef int8_t INT8;
typedef uint8_t UINT8;
typedef char CHAR8;
typedef unsigned short CHAR16;
typedef unsigned char BOOLEAN;
typedef void VOID;
BUG=b:118775313
TEST=Build and boot grunt.
Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add an `amdblocks` internal API and rename
soft_reset() => warm_reset()
hard_reset() => cold_reset()
as these terms are commonly used in the surrounding code.
On Stoney Ridge, make board_reset() call cold_reset() to keep
current behaviour of common code calling hard_reset(). But add
a TODO if this is intended.
Note: Stoney Ridge is using CF9 for the actual reset but the
configuration for a cold reset doesn't use the usual full reset
bit but some other mechanism.
Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Eliminate the references to PspBaseLib.c and PspBaseLib.h in
agesa_headers.h. Fix psp.c references to definitions in those files
by adding them to include/amdblocks/psp.h.
BUG=b:78514564
TEST=Build and boot grunt/ChromeOS and restore an image from the internet.
Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a
Signed-off-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27619
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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STAPM programming was created inside function OemCustomizeInitEarly().
It should be SOC specific, and called by agesawrapper just before the
call to OemCustomizeInitEarly().
BUG=b:116196626
TEST=build and boot grunt
Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28705
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In preparation to removing AmdLib, function LibAmdLocateImage() has to be
ported to be used by agesawrapper. The most important aspect of this porting
is that it has to obey coreboot format, specifically 8 character tab and 80
characters max. This required breaking the function in 2 (to solve
indentation) and rename some variables to shorter names.
One important aspect was breaking
(AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset)
into:
image_ptr = (AMD_IMAGE_HEADER *) current_ptr;
if (validate_image((void *)image_ptr->ModuleInfoOffset,
and, within validate_image completed by:
AMD_MODULE_HEADER *mod_ptr = (AMD_MODULE_HEADER *)module_chain;
BUG=b:112625809
TEST=Build grunt, functionality tested in next commit.
Change-Id: I0d1e8b966cf7606fdb15a95de5771f835f07b2bc
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Per AMD, the Integrated Micro Controller is not a supported feature of
the Stoney Ridge APU. Systems are expected to implement an external EC
for desired features. Remove all stoney IMC files and functions from
src/soc/amd/stoneyridge.
There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG
describe these bits, so a new patch will be released later to fix the
names and comment.
BUG=b:111780177
TEST=Build grunt and gardenia
Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27651
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, create code that allows changing eDP training parameter.
BUG=b:111673328
TEST=Tested in child patch.
Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Implement an optional callout for AgesaHeapRebase which allows AGESA
to override any internal hardcoded heap addresses.
Designate a region in CAR that may be used for pre-mem heap and return
that address before DRAM is configured. After DRAM is up, the address
in cbmem is returned.
TEST=Boot grunt with patchstack and experimental blob
BUG=b:74518368
Change-Id: Ieda202a6064302b21707bd7ddfabc132cd85ed45
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Implement a new AGESA callout that may be used to find the correct
temporary location in DRAM to store heap data.
Near the end of AmdInitPost, AGESA migrates its heap from a CAR-based
location to a temporary region. Once cbmem has been established, the
heap will be relocated again in AmdInitEnv from the temp location to
the final one.
This patch does not materially affect the behavior of AGESA's heap
management. It only puts coreboot in control of the location. Future
work may refactor the copying.
TEST=Boot grunt with patchstack and experimental blob
BUG=b:74518368
Change-Id: Ibc5cc988e3e80d78f50cf0195e952b657141e570
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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It was decided to not add the buffers definitions, so the todo message
is obsolete. Replace it with minimum instructions about when a new buffer
will be needed.
It was also noticed a typo in one command. MBOX_BIOS_CMD_C3_DATA_INFO is
about S3 transition, so it should be called MBOX_BIOS_CMD_S3_DATA_INFO.
BUG=b:77940747
TEST=None.
Change-Id: I6143d7e85476061395962b95ad8864ac32a1d4a3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25740
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert agesa_heap_base() to static since it's unused outside of
heapmanager.c.
Change-Id: I3ee162985ca1ea36461ea413416d98451a700f8c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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It was required for all cores use the same CAR teardown function
(exit_car.S and gcccar.inc). AGESA has already been modified to do the
AP to do the call out. Create assembly code to call chipset_teardown_car
and then enter an endless loop with halt instruction. Then create the
call out that will call this new assembly code.
BUG=b:70338633
AGESA COMMIT=3313d277
TEST=Created a debug version of AGESA that would print the returned
status of HALT_THIS_AP. Build code without the fix, see the return.
Build code with the fix, see that there's no return.
Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/24999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add new functions that can execute InitRtb, InitResume, LateResume,
and FinalResume.
Note that the name AmdInitRtb supersedes the deprecated AmdS3Save.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add functions that the wrapper will call to get and save the S3 data.
The wrapper requires two types of data saved:
* Non-volatile: Information that is the minimum required for bringing
the DRAM controller back online. This change uses the common
mrc_cache driver to manage the storage
* Volatile: May be stored in DRAM; information required to complete
the system restoration process.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Revert most of 4f3f47b "amd/common: Define regions in cbmem". This
puts the management of the heap space back to its traditional
methodology. Subsequent patches that were to have used these
subregions have been reworked.
BUG=b:69614064
Change-Id: Ib3d40bcf61c50dbc481b60e7b5286f65a529b912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The cbmem location holding the heap will be used to store additional
information in subsequent patches. Remove the static designation from
agesa_heap_base.
Change-Id: Ic607432fd6500ef69b5d47793896cf12a699d8b7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22721
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In 6c747068 "amd/stoneyridge: Put AGESA heap into cbmem" the AGESA
heap was moved completely into cbmem. This was a departure from the
"late cbmem init" method of adding it late in post, then storing the
S3 volatile data to the region. Remove the hardcoded base address
that was missed in that commit.
To prepare for S3 support, split the region into subregions for
heap, AGESA's S3 volatile storage, and an MTRR save area.
BUG=b:69614064
Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the original spi.c file that writes S3 NV data to flash in a
proprietary format. The s3 folder is retained to facilitate new
development.
Change-Id: I1b5fe8e854c3d2dd71506c2acd6ff73e4b86d7d4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b.
This is not the correct fix for the heap allocator.
It looks like the root cause is in the buffer size of the
deallocate function.
Change-Id: I33c479a30d89a665677d3e4914194ae8136504af
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The heap allocator would try to split a buffer node that
was too small for another node. In the failing case, the buffer
node was 0x140 bytes and the requested size was 0x133 bytes.
The logic would check that there was room for the header and
buffer and try to split the buffer node. The buffer node header
is 0xC bytes, so 0x13F bytes are need. The problem is that it didn't
leave room for another node header and a little space for a buffer.
BUG=b:71764350
TEST= Boot grunt.
BRANCH=none
Change-Id: Iece5e12d5787415a335bb953985331a5dc312152
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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